VRCPBF16

VRCPBF16 estimates 1/x for each bfloat16 value, 8, 16 or 32 per register, with a relative error below 2^-8 + 2^-14 by the AVX10.2 specification (revision 7.0). A bfloat16 has 8 significant bits, so 2^-8 is half a unit in the last place for a significand near 1: like VRCPPH for halves, the estimate is close to the correctly rounded reciprocal and leaves nothing for a Newton-Raphson step to gain. It belongs to AVX10.2; the opcode is 4Ch in EVEX map 6 with no prefix and W0, where VRCPPH has 66, and the source may be broadcast from 16 bits of memory.

Special inputs#

The specification’s table maps exact powers of two to exact powers of two and the infinities to zeros of their sign. Denormals are read as zeros, so they and the zeros give an infinity of their sign, and the routine also flushes denormal results: 1/x for x above 2^126 would be a denormal and becomes zero.

The entry does not carry the sentence that VADDBF16’s and most other bfloat16 entries carry, that the instruction raises no floating-point exceptions and neither reads nor updates MXCSR, and the bfloat16 chapter has no general section that would say it for all of them. The entry still places VRCPBF16 in exception class E4, which Section 4.2.5 defines for vector instructions that cause no SIMD floating-point exceptions, and its routine names DAZ and FTZ, not MXCSR’s bits.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles _mm512_rcp_pbh to VRCPBF16, but never uses it for C: 1 / X[i] and X[i] / Y[i] over global __bf16 arrays stay VDIVBF16 even with -ffast-math. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.bf16[i] = rcp(src2.bf16[i])
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# rcp: 1/a within 2^-8 + 2^-14
# BF16: denormals flushed, in and out, no flags; MXCSR unused
# m16bcst: src2.bf16[i] is the m16 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCPBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions