VRCPPH

VRCPPH estimates 1/x for each half, 32 per zmm register, with a relative error below 2^-11 + 2^-14 by Intel’s manual. That is hardly more than the rounding error of a half, which has 11 significant bits: the estimate is nearly the correctly rounded reciprocal, where VRCP14PS for singles is good to 14 of 24 bits and needs a Newton-Raphson step. The opcode is 4Ch in EVEX map 6 with the 66 prefix, VRCP14PS’s byte in 0F38; it takes no rounding mode, sets no MXCSR flag and raises no SIMD exception. VADDPH covers the format and the CPUID bits.

No Newton step#

Intel’s optimization manual puts numbers on it (Sections 18.5.8.1 and 18.5.8.2): VRCPPH is within 0.5 ULP for 98% of inputs and within 0.5625 ULP for the rest, so a Newton step would gain nothing. On the processor it describes it takes 4 cycles at up to 256 bits and 6 at 512, against 15 and 24 for a division by VDIVPH, and a quotient taken as a times VRCPPH(b) is about three times faster than the division and within about 1.5 ULP, except for divisors near either end of the range.

Intel’s table of special inputs maps exact powers of two to exact powers of two and the infinities to zeros of their sign. Denormals are handled, not flushed: only those up to 2^-16 give infinity, since their reciprocals pass 65504; the larger denormals have a finite reciprocal.

In our builds#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16 keep 1 / a[i] over _Float16 arrays a VDIVPH. With -ffast-math both replace it by VRCPPH alone, and a[i] / b[i] by VRCPPH and VMULPH, with no refinement step, unlike the float loops on VRCP14PS’s page. On a single value with -ffast-math, Clang emits VRCPSH and GCC keeps VDIVSH. The intrinsic _mm512_rcp_ph gives it in both. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRCPPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = rcp(src2.f16[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# rcp: 1/a within 2^-11 + 2^-14; denormals kept; no flags
# m16bcst: src2.f16[i] is the m16 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCPPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPTESTNMQ
• VPTESTNMW
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD

All 686 AVX10.1 instructions