VRCPPS instruction (AVX)

VRCPPS estimates 1/x for each single, four in an xmm register and eight in a ymm one: the VEX form of RCPPS, with a separate destination and the bits above the result cleared. Both vendors’ manuals promise a relative error of at most 1.5 × 2^-12, about 11 correct bits, and not which bits, so the estimate may differ between processors. MXCSR’s rounding field plays no part, and no flag is ever set.

The estimate on Zen 5

Zen 5’s estimate is not exact even for powers of two: with MXCSR 0, 1 gave 0.999755859375 (3F7FF000H), 2 gave 0.4998779296875 and 0.5 gave 1.99951171875, each too small by 2^-12 of the true value. AVX-512’s VRCP14PS, accurate to 2^-14, returned 2.0 and 0.5 exactly.

Zeros, denormals and tiny results

Both manuals treat a denormal input as a zero and flush a tiny result to zero, whatever DAZ and FTZ say. The recorded cases agree:

+0 and -0 gave +infinity and -infinity, and denormals with DAZ set gave infinities of their sign;
the largest single gave +0 and the most negative -0 with FTZ clear, where the true reciprocals are denormal (VRCP14PS returns those as denormals);
infinities gave zeros of their sign; NaNs came back quiet, without IE or #XM even with every exception unmasked.

Division by estimate

With -ffast-math, GCC 14 and Clang 23 at -O2 for -march=x86-64-v3 compile a[i] / b[i] over floats to VRCPPS, one Newton-Raphson step, r’ = r(2 - b r), and a multiplication by a[i]: GCC writes the step with VMULPS, VADDPS and VSUBPS, Clang with VFMSUB213PS and VFNMADD132PS. The step brings the quotient close to single precision, but it starts from the processor’s estimate, so the last bit can differ between processors, where VDIVPS is always correctly rounded.

There is no EVEX form; AVX-512 code uses VRCP14PS, which also has a double version and masking.

Forms

Every encoding of VRCPPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRCPPS xmm, m128` VRCPPS_XMMdq_MEMdq	`VEX.128.NP.0F.WIG 53 /r`	AVX
`VRCPPS xmm, xmm` VRCPPS_XMMdq_XMMdq	`VEX.128.NP.0F.WIG 53 /r`	AVX
`VRCPPS ymm, m256` VRCPPS_YMMqq_MEMqq	`VEX.256.NP.0F.WIG 53 /r`	AVX
`VRCPPS ymm, ymm` VRCPPS_YMMqq_YMMqq	`VEX.256.NP.0F.WIG 53 /r`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Every single works alike: 4 and 8 singles in the xmm and ymm forms.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    ymm1.f32[i] = rcp(src2.f32[i])
# rcp: 1/a within 1.5 * 2^-12; Zen 5's 6
# recorded results: 1.0000 * 2^-12 at most
# a denormal is a zero, and so is a result below 2^-126
# (in Zen 5's cases, from |a| = 2^127 up), whatever
# MXCSR says; no flags
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRCPPS xmm, xmm/m128` `VRCPPS ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rcp_ps` `__m128 _mm_rcp_ps(__m128 __a)`	`VRCPPS xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_rcp_ps` `__m256 _mm256_rcp_ps(__m256 __a)`	`VRCPPS ymm, ymm` VEX.256 -mavx

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

The estimate on Zen 5#

Zeros, denormals and tiny results#

Division by estimate#