VRCPSH instruction (AVX10.1)

VRCPSH estimates the reciprocal of the low half of its second source, with a relative error below 2^-11 + 2^-14, and copies bits 127:16 from the first source, clearing the bits above 127. It is the scalar form of VRCPPH, whose page gives the accuracy Intel’s optimization manual measured, within 0.5 ULP for 98% of inputs and 0.5625 ULP for the rest, and the special inputs: powers of two give exact powers of two, infinities zeros, and only the denormals up to 2^-16 overflow to infinity. The encoding is 4Dh with the 66 prefix in EVEX map 6, VRCP14SS’s byte in 0F38, with a write mask on the low half and a two-byte memory operand. There is no rounding mode, and Intel’s entry lists no SIMD exception: the estimate sets no MXCSR flag. VADDPH covers the format and the CPUID bits, and VRSQRTSH estimates a reciprocal square root.

Where it replaces a division

At -O2 with -march=x86-64-v4 -mavx512fp16 and -ffast-math, Clang 23 compiles 1 / x on a _Float16 value to vrcpsh xmm0, xmm0, xmm0 and x / y to VRCPSH and VMULSH, as VDIVSH’s page shows, with no Newton-Raphson step. GCC 14 keeps VDIVSH for both, though it vectorizes the same loops over arrays with VRCPPH. Without that option neither compiler emits it except for _mm_rcp_sh(a, b), which becomes vrcpsh xmm0, xmm0, xmm1, the estimate for the low half of b with the rest of a.

The manual’s advice for the packed form holds here too (Sections 18.5.8.1 and 18.5.8.2): for a half the estimate is so close that a refinement step gains nothing, and a quotient computed as a times the estimate of 1/b is within about 1.5 ULP of the true one, except for divisors near either end of the range.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRCPSH.

Forms

Every encoding of VRCPSH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRCPSH xmm {k}{z}, xmm, xmm` VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512	`EVEX.LIG.66.MAP6.W0 4D /r`	AVX10.1 or AVX512_FP16
`VRCPSH xmm {k}{z}, xmm, m16` VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512	`EVEX.LIG.66.MAP6.W0 4D /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm`	`xmm {k}{z}, xmm, m16`
Sapphire Rapids	4 / 1p0	11 / 1p0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low half is computed; the other halves come from xmm2.

The write mask k1 applies to the low half: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result half 0 is computed from half 0 of xmm3; halves 7 to 1 are those of xmm2. Result halves 7 to 0: a7, a6, a5, a4, a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = rcp(src3.f16[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# rcp: 1/a within 2^-11 + 2^-14; denormals kept; no flags
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRCPSH xmm {k}{z}, xmm, xmm/m16`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms: write masking
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRCPSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rcp_sh` `__m128h _mm_rcp_sh(__m128h __A, __m128h __B)`	`VRCPSH xmm, xmm, xmm` EVEX.LIG -mavx512fp16
`_mm_mask_rcp_sh` `__m128h _mm_mask_rcp_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B)`	`VRCPSH xmm {k}, xmm, xmm` EVEX.LIG -mavx512fp16
`_mm_maskz_rcp_sh` `__m128h _mm_maskz_rcp_sh(__mmask8 __U, __m128h __A, __m128h __B)`	`VRCPSH xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Where it replaces a division#