VREDUCEPD

VREDUCEPD returns, for each double x, x minus x rounded to M fraction bits, M being bits 7:4 of the immediate: what rounding takes away. It is the double form of VREDUCEPS, whose page shows how the rounding direction sets the range of the result and how the result and VRNDSCALEPD’s add up to x. Like it, it needs AVX512DQ, takes a mask, a broadcast and, at 512 bits, {sae}, and the scalar form is VREDUCESD.

Recorded on Zen 5#

• Halves. With immediate 18h, M = 1 and rounding to nearest without a precision exception, x keeps what lies beyond a multiple of 1/2: 41DFFFFFFFFFFFFFh, 2^31 - 2^-22, gave -2^-22, as it rounds up to 2^31; 0.1 came back unchanged, as it rounds to 0; -2.5 and 2^31 - 1 gave 0.
• Zeros and infinities. +infinity gave +0 with immediate 10h, and -0 gave +0 with F8h, M = 15 rounding to nearest, the same as the single cases on VREDUCEPS’s page. No case changed MXCSR.

In compiled code#

GCC 14 and Clang 23 at -O2 emit VREDUCEPD only for the intrinsics, such as _mm512_reduce_pd(x, imm). A loop of a[i] - nearbyint(a[i]) over double arrays, with -march=x86-64-v4, is VRNDSCALEPD and VSUBPD in GCC and VROUNDPD and VSUBPD on YMM registers in Clang; a[i] - floor(a[i]) stays scalar VRNDSCALESD in GCC unless -ffast-math is given, and for infinities none of these equals VREDUCEPD’s +0.

AMD’s Zen 5 latency spreadsheet gives VREDUCEPD two macro-ops with a latency of 6 cycles on pipes FP2 and FP3, one per cycle, and four macro-ops from memory, as VREDUCEPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.f64[i] = reduce(a, imm8)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCEPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS

All 686 AVX10.1 instructions