VREDUCEPH

VREDUCEPH returns, for each half, what rounding to M fraction bits takes away: x minus x rounded to a multiple of 2^-M, where M is bits 7:4 of the immediate and the low four bits choose the rounding as for VRNDSCALEPS. It is the FP16 form of VREDUCEPS, whose page explains the ranges that each rounding direction gives and the special results: +0 for an infinity and, except when rounding down, for an exact multiple. The opcode is that of VREDUCEPS, 56h in map 0F3A, with no prefix instead of 66, and it takes masking, a broadcast half and {sae}. VADDPH covers the format and the CPUID bits, and VREDUCESH is the scalar form.

Few fraction bits#

A half has only 10 fraction bits, so from 1024 up every half is an integer and from 2^(10-M) up every half is a multiple of 2^-M: there VREDUCEPH returns zero. Intel’s table of special cases also shows results that are not exact. For a small positive input rounded up, the result is the input minus 2^-M, which needs a rounding of its own; the same happens for a small negative input rounded down.

Argument reduction#

Intel’s optimization manual lists VREDUCE with VGETEXP, VGETMANT, VSCALEF, VFPCLASS and VRNDSCALE as the FP16 instructions that help implement math libraries, and defines it as x minus VRNDSCALE of x with the same immediate (Section 18.7); for exp2 and pow, the fraction x - floor(x) that it computes in one step feeds the polynomial (Section 17.15.4).

In our builds#

GCC 14 and Clang 23 emit VREDUCEPH only for the intrinsics, such as _mm512_reduce_ph(x, imm). With -march=x86-64-v4 -mavx512fp16 at -O2, a loop of a[i] - truncf16(a[i]) stays a rounding and a subtraction, also with -ffast-math: VRNDSCALEPH and VSUBPH in Clang, and in GCC scalar VRNDSCALESH and VSUBSH, or the packed pair with that option.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VREDUCEPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.f16[i] = reduce(a, imm8)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCEPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD

All 686 AVX10.1 instructions