VREDUCEPS

VREDUCEPS returns what rounding takes away: for each single x it computes x minus x rounded to M fraction bits, where M is bits 7:4 of the immediate. Its low four immediate bits are those of VRNDSCALEPS, whose page lists them: the rounding direction, MXCSR’s mode instead, and no precision exception. So with the same immediate, VRNDSCALEPS gives the rounded part and VREDUCEPS the rest, and the two add up to x exactly. It belongs to AVX512DQ, with VREDUCEPD and the scalar VREDUCESS and VREDUCESD.

The rounding direction sets the range#

With M = 0, rounding down gives x - floor(x), in [0, 1); to nearest gives a remainder in [-1/2, 1/2]; up gives (-1, 0]. Each M halves these. Cases recorded on Zen 5 show the edges: to nearest even, 1.5 gave -0.5 and 2.5 gave 0.5, as the ties went to 2; rounding down, an integer such as 2.0 gave -0, not +0. An infinity gives +0, where the subtraction would give a NaN, and so does -0 unless rounding down: Zen 5 returned +0 for -0 and both infinities; a NaN comes back quiet, setting IE if it was signaling.

Argument reduction#

Intel’s optimization manual names exp2 and pow as the main uses (Sections 17.15.4 and 17.15.5): 2^x is 2^n times 2^f, where n is an integer and f = x - floor(x) is VREDUCEPS with rounding down. A polynomial or a small table gives 2^f, and VSCALEFPS multiplies it by 2 to the power floor(x) taken straight from x, handling overflow, underflow and infinities without a separate path.

In compiled code#

GCC 14 and Clang 23 emit VREDUCEPS only for the intrinsics, such as _mm512_reduce_ps(x, imm), with AVX512DQ enabled. A loop of x - floorf(x) stays VRNDSCALEPS and VSUBPS in Clang and scalar VRNDSCALESS in GCC, even with -ffast-math for znver5, and for infinities that is not the same result.

AMD’s Zen 5 guide lists VREDUCEPS as two macro-ops with a latency of 6 cycles, four macro-ops from memory, against one macro-op and 3 cycles for VRNDSCALEPS and 2 for VSUBPS, so on Zen 5 the single instruction saves an instruction but not latency.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.f32[i] = reduce(a, imm8)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCEPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH

All 686 AVX10.1 instructions