VREDUCESD

VREDUCESD returns what rounding takes from the low double of its second source: x minus x rounded to a multiple of 2^-M, M being bits 7:4 of the immediate, with the rounding direction and the precision control of VRNDSCALESD’s immediate in bits 3:0. With the same immediate the two results add up to x. Bits 127:64 come from the first source, and a write mask decides only the low double. It is the scalar form of VREDUCEPD, and VREDUCEPS explains the range each rounding direction gives and the special results: +0 for an infinity, and a quieted NaN. It came with AVX512DQ; the second source is an XMM register or 8 bytes of memory, and the register form takes {sae}.

Recorded on Zen 5#

• Rounding up. In vreducesd xmm14{k3}, xmm8, xmm29, {sae}, 0x2, M = 0 and rounding up, 2.5 gave -0.5, that is 2.5 - 3, and the upper double came from XMM8; MXCSR stayed unchanged.
• Zeroing. With bit 0 of K6 clear, vreducesd xmm17{k6}{z}, xmm30, qword ptr [...], 0xf3 cleared the low double and kept the upper one of XMM30.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VREDUCESD only for the intrinsics: _mm_reduce_sd(a, b, 0x11) is one instruction. x - floor(x) on one double rounds with VRNDSCALESD in GCC and VROUNDSD in Clang, then subtracts with VSUBSD; for an infinity, that gives a NaN instead of VREDUCESD’s +0.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP2 and FP3 and 6 cycles, one per cycle, and four macro-ops from memory, the figures of VREDUCEPD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f64[0] = reduce(src3.f64[0], imm8)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCESD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS

All 686 AVX10.1 instructions