VREDUCESH

VREDUCESH returns what rounding takes from the low half of its second source: x minus x rounded to a multiple of 2^-M, M being bits 7:4 of the immediate, with the rounding direction and the precision control of VRNDSCALESH’s immediate. Bits 127:16 come from the first source and the bits above 127 are cleared. It is the scalar form of VREDUCEPH, whose page covers the special results and the inexact cases that FP16’s 10 fraction bits bring, and of which VREDUCEPS explains the ranges each rounding direction gives. VADDPH covers the format and the CPUID bits.

Encoding and flags#

The opcode is 57h in the 0F3A map with no prefix, where VREDUCESS has 66: FP16’s instructions with an immediate stay in that map. VREDUCESH takes a write mask on the low half, {sae} and a two-byte memory operand. Intel’s entry lists only invalid and precision, the latter silenced by bit 3 of the immediate, and notes that a tiny nonzero result reports no underflow, even with the underflow exception unmasked.

Argument reduction in one step#

Intel’s optimization manual defines VREDUCE as x minus VRNDSCALE of x with the same immediate and names it for the argument reduction of exp2 and pow (Section 18.7). For a single half, our compilers do not form it from C: at -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile x - truncf16(x) and x - floorf16(x) to VRNDSCALESH with 0Bh or 09h and a VSUBSH, also with -ffast-math. The intrinsic _mm_reduce_sh(a, b, 0x10), one fraction bit to nearest, gives vreducesh xmm0, xmm0, xmm1, 16 in both.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VREDUCESH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = reduce(src3.f16[0], imm8)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCESH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD

All 686 AVX10.1 instructions