VREDUCESS

VREDUCESS returns what rounding takes from the low single of its second source: x minus x rounded to a multiple of 2^-M, M being bits 7:4 of the immediate, while bits 3:0 choose the rounding direction, MXCSR’s mode instead, and no precision exception, as in VRNDSCALESS’s immediate. Bits 127:32 come from the first source, and a write mask decides only the low single. It is the scalar form of VREDUCEPS, whose page explains the range each rounding direction gives, the special results and the use in exp2 and pow; VREDUCESD is the double form and VREDUCESH the half-precision one. It came with AVX512DQ, takes an XMM register or 4 bytes of memory as its second source, and {sae} in the register form.

Recorded on Zen 5#

• A quiet NaN. vreducess xmm0{k2}{z}, xmm31, dword ptr [...], 0x18 returned the quiet NaN FFC00005h unchanged, without a flag, and the three singles above it came from XMM31.
• Merging. With bit 0 of K1 clear, vreducess xmm24{k1}, xmm3, xmm3, {sae}, 0x22 kept the old low single of XMM24 and took the upper three from XMM3.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 emit VREDUCESS only for the intrinsics, such as _mm_reduce_ss(a, b, 0x11). x - nearbyintf(x) rounds with VRNDSCALESS in GCC and VROUNDSS in Clang, then subtracts with VSUBSS.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP2 and FP3 and 6 cycles, one per cycle, and four macro-ops from memory, as for VREDUCESD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f32[0] = reduce(src3.f32[0], imm8)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VREDUCESS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS

All 686 AVX10.1 instructions