VRNDSCALEBF16

VRNDSCALEBF16 rounds each bfloat16 value to a multiple of 2^-M, where M is bits 7:4 of the immediate, 8, 16 or 32 per register. With M = 0 it rounds to an integer. It belongs to AVX10.2; the opcode is 08h in map 0F3A with the F2 prefix and W0, where VRNDSCALEPH has no prefix, and the source may be broadcast from 16 bits of memory. EVEX.vvvv must be 1111b. A NaN comes back quiet, the sign is kept, -0 included, and a denormal is read as zero first. VREDUCEBF16 returns what the rounding removes.

Nearest even only#

VRNDSCALEPS’s page lists the low immediate bits that choose floor, ceiling, truncation or MXCSR’s mode. The AVX10.2 specification (revision 7.0) opens VRNDSCALEBF16’s description by saying that the immediate chooses the rounding mode, but the rest of the entry says round to nearest even is used, and its routine reads only bits 7:4. So the instruction cannot compute floor or trunc directly. Every bfloat16 from 128 up is an integer, since the format has 7 fraction bits, and every one from 2^(7-M) up a multiple of 2^-M.

Like VRCPBF16’s entry, this one lacks the sentence on exceptions and MXCSR that VADDBF16’s entry has, and relies on exception class E4, defined in Section 4.2.5 as causing no SIMD floating-point exceptions.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles _mm512_roundscale_pbh(x, 0x10) to vrndscalebf16 zmm0, zmm0, 16, and passes the immediate of the masked form through unchanged, 1Bh included. Loops of __builtin_elementwise_floor, trunc and even roundeven, which matches the instruction with M = 0, over global __bf16 arrays do not use it: each element is widened, rounded with VROUNDSS and immediate 9, 11 or 8, and narrowed with VCVTNEPS2BF16, with or without -ffast-math. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.bf16[i]
        zmm1.bf16[i] = rndscale(a, imm8)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m16bcst: src2.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; always rounds to nearest even; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions