VRNDSCALEPD

VRNDSCALEPD rounds each double to a multiple of 2^-M, where M is bits 7:4 of the immediate, from 0 to 15, in the direction its low four bits choose. It is the double form of VRNDSCALEPS, whose page lists the immediates behind floor, ceil, trunc, nearbyint and rint, and the AVX-512 counterpart of VROUNDPD, which has no ZMM form and no mask. With 52 fraction bits, a double of magnitude 2^(52-M) or more is already a multiple and comes back unchanged.

Recorded on Zen 5#

• Fraction bits. Under 0F8h, 15 fraction bits to nearest, vrndscalepd ymm17{k2}{z}, ymm30, 0xf8 returned the largest double and -1.0 unchanged, and zeroed the two elements that 9h, the low bits of K2, left out.
• NaNs and zeros. A quiet NaN with the payload 12345h, broadcast in vrndscalepd zmm24{k2}, qword bcst [mem], 0xf3, came back with the same bits, and under 33h +0 and -0 kept their signs.
• MXCSR kept its value in all 6 cases, its flags included.

In compiled code#

The compilers treat doubles as singles. GCC 14 at -O2 with -march=x86-64-v4 vectorizes a loop of nearbyint into VRNDSCALEPD with 0Ch on ZMM registers but rounds floor and trunc one element at a time with VRNDSCALESD, 09h and 0Bh, also for -march=znver5. Clang 23 vectorizes all three, with VROUNDPD on YMM registers for x86-64-v4 and VRNDSCALEPD on ZMM for znver5; it also turns _mm256_roundscale_pd(x, 1) into VROUNDPD and keeps VRNDSCALEPD for the ZMM intrinsics and wherever M is above 0.

AMD’s Zen 5 latency spreadsheet gives VRNDSCALEPD 3 cycles and two per cycle on pipes FP2 and FP3, as VRNDSCALEPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = src2.f64[i]
        zmm1.f64[i] = rndscale(a, imm8)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m64bcst: src2.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD

All 686 AVX10.1 instructions