x86-64.net

Instruction

VRNDSCALEPD

Rounds packed doubles to the number of fraction bits and with the rounding mode that an immediate gives.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VRNDSCALEPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VRNDSCALEPD zmm {k}{z}, zmm, imm8, {sae} VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512EVEX.512.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F
VRNDSCALEPD zmm {k}{z}, m512/m64bcst, imm8 VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512EVEX.512.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F
VRNDSCALEPD xmm {k}{z}, xmm, imm8 VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512EVEX.128.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F + AVX512VL
VRNDSCALEPD xmm {k}{z}, m128/m64bcst, imm8 VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512EVEX.128.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F + AVX512VL
VRNDSCALEPD ymm {k}{z}, ymm, imm8 VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512EVEX.256.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F + AVX512VL
VRNDSCALEPD ymm {k}{z}, m256/m64bcst, imm8 VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512EVEX.256.66.0F3A.W1 09 /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_roundscale_pd __m128d _mm_mask_roundscale_pd(__m128d W, __mmask8 U, __m128d A, const int imm)

VRNDSCALEPD xmm {k}, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_roundscale_pd __m128d _mm_maskz_roundscale_pd(__mmask8 U, __m128d A, const int imm)

VRNDSCALEPD xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512vl

_mm256_mask_roundscale_pd __m256d _mm256_mask_roundscale_pd(__m256d W, __mmask8 U, __m256d A, const int imm)

VRNDSCALEPD ymm {k}, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_roundscale_pd __m256d _mm256_maskz_roundscale_pd(__mmask8 U, __m256d A, const int imm)

VRNDSCALEPD ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512vl

_mm512_ceil_pd __m512d _mm512_ceil_pd(__m512d __A)

VRNDSCALEPD zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_floor_pd __m512d _mm512_floor_pd(__m512d __A)

VRNDSCALEPD zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_roundscale_pd __m512d _mm512_roundscale_pd(__m512d A, const int B)

VRNDSCALEPD zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_roundscale_round_pd __m512d _mm512_roundscale_round_pd(__m512d A, const int imm, const int R)

VRNDSCALEPD zmm, zmm, imm8, {sae} EVEX.512 -mavx512f

_mm512_mask_ceil_pd __m512d _mm512_mask_ceil_pd(__m512d __W, __mmask8 __U, __m512d __A)

VRNDSCALEPD zmm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_floor_pd __m512d _mm512_mask_floor_pd(__m512d __W, __mmask8 __U, __m512d __A)

VRNDSCALEPD zmm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_roundscale_pd __m512d _mm512_mask_roundscale_pd(__m512d A, __mmask8 B, __m512d C, const int imm)

VRNDSCALEPD zmm {k}, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_roundscale_round_pd __m512d _mm512_mask_roundscale_round_pd(__m512d A, __mmask8 B, __m512d C, const int imm, const int R)

VRNDSCALEPD zmm {k}, zmm, imm8, {sae} EVEX.512 -mavx512f

_mm512_maskz_roundscale_pd __m512d _mm512_maskz_roundscale_pd(__mmask8 A, __m512d B, const int imm)

VRNDSCALEPD zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_roundscale_round_pd __m512d _mm512_maskz_roundscale_round_pd(__mmask8 A, __m512d B, const int imm, const int R)

VRNDSCALEPD zmm {k}{z}, zmm, imm8, {sae} EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.