VRNDSCALEPH

VRNDSCALEPH rounds each half to a multiple of 2^-M, where M is bits 7:4 of the immediate, 32 per zmm register. Its immediate is that of VRNDSCALEPS, whose page lists the values that C’s floor, ceil, trunc, nearbyint and rint use: bits 1:0 choose the direction, bit 2 takes MXCSR’s rounding mode instead and bit 3 suppresses the precision exception. Infinities, zeros and values that are already multiples come back unchanged and NaNs come back quiet. It takes masking, a source broadcast from one half and {sae}, and has no other source: EVEX.vvvv must be 1111b. VADDPH covers the format and the CPUID bits; VRNDSCALESH is the scalar form and VREDUCEPH returns what the rounding removes.

Encoding and range#

Like FP16’s other instructions with an immediate, VRNDSCALEPH stays in the 0F3A map: opcode 08h with no prefix, where VRNDSCALEPS has 66, as VGETMANTPH’s page explains. Halves from 1024 up are all integers, so there M = 0 changes nothing. At the other end Intel’s entry lists underflow among its exceptions, which the single-precision entry does not: with M = 15 the results are multiples of 2^-15, half the smallest normal half, so a rounded result can be a denormal. The manual’s math-library section names VRNDSCALE for argument reduction, lookup-table indices and floor, ceiling and truncation (Intel’s optimization manual, Section 18.7).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 vectorizes loops of __builtin_floorf16, ceilf16, truncf16 and rintf16 over global _Float16 arrays to VRNDSCALEPH on ymm registers with the immediates 09h, 0Ah, 0Bh and 04h, the source read from memory, and a narrowed (_Float16)nearbyintf((float)x) with 0Ch. GCC 14 vectorizes the rint and nearbyint loops on zmm registers, but keeps the floor, ceiling and truncation loops scalar, with VRNDSCALESH, unless -ffast-math is given. roundf16, which rounds halfway cases away from zero, is a library call in GCC without that option; Clang adds the half just below 0.5, 0.49976, with the sign of x copied by a VPTERNLOGQ, and truncates the sum with 0Bh. The intrinsic _mm512_roundscale_ph(x, 0x13), one fraction bit and toward zero, is a plain VRNDSCALEPH in both.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRNDSCALEPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = src2.f16[i]
        zmm1.f16[i] = rndscale(a, imm8)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m16bcst: src2.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPUNPCKLWD
• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS

All 686 AVX10.1 instructions