x86-64.net

Instruction

VRNDSCALEPH

Rounds packed half-precision values to the number of fraction bits and with the rounding mode that an immediate gives.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VRNDSCALEPH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VRNDSCALEPH xmm {k}{z}, xmm, imm8 VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VRNDSCALEPH xmm {k}{z}, m128/m16bcst, imm8 VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VRNDSCALEPH ymm {k}{z}, ymm, imm8 VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VRNDSCALEPH ymm {k}{z}, m256/m16bcst, imm8 VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16 + AVX512VL
VRNDSCALEPH zmm {k}{z}, zmm, imm8, {sae} VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16
VRNDSCALEPH zmm {k}{z}, m512/m16bcst, imm8 VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 08 /r ibAVX10.1 or AVX512_FP16

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_roundscale_ph __m128h _mm_roundscale_ph(__m128h A, const int imm)

VRNDSCALEPH xmm, xmm, imm8 EVEX.128 -mavx512fp16 -mavx512vl

_mm_mask_roundscale_ph __m128h _mm_mask_roundscale_ph(__m128h W, __mmask8 U, __m128h A, const int imm)

VRNDSCALEPH xmm {k}, xmm, imm8 EVEX.128 -mavx512fp16 -mavx512vl

_mm_maskz_roundscale_ph __m128h _mm_maskz_roundscale_ph(__mmask8 U, __m128h A, const int imm)

VRNDSCALEPH xmm {k}{z}, xmm, imm8 EVEX.128 -mavx512fp16 -mavx512vl

_mm256_roundscale_ph __m256h _mm256_roundscale_ph(__m256h A, const int imm)

VRNDSCALEPH ymm, ymm, imm8 EVEX.256 -mavx512fp16 -mavx512vl

_mm256_mask_roundscale_ph __m256h _mm256_mask_roundscale_ph(__m256h W, __mmask16 U, __m256h A, const int imm)

VRNDSCALEPH ymm {k}, ymm, imm8 EVEX.256 -mavx512fp16 -mavx512vl

_mm256_maskz_roundscale_ph __m256h _mm256_maskz_roundscale_ph(__mmask16 U, __m256h A, const int imm)

VRNDSCALEPH ymm {k}{z}, ymm, imm8 EVEX.256 -mavx512fp16 -mavx512vl

_mm512_roundscale_ph __m512h _mm512_roundscale_ph(__m512h A, const int B)

VRNDSCALEPH zmm, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_roundscale_round_ph __m512h _mm512_roundscale_round_ph(__m512h A, const int imm, const int R)

VRNDSCALEPH zmm, zmm, imm8, {sae} EVEX.512 -mavx512fp16

_mm512_mask_roundscale_ph __m512h _mm512_mask_roundscale_ph(__m512h A, __mmask32 B, __m512h C, const int imm)

VRNDSCALEPH zmm {k}, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_mask_roundscale_round_ph __m512h _mm512_mask_roundscale_round_ph(__m512h A, __mmask32 B, __m512h C, const int imm, const int R)

VRNDSCALEPH zmm {k}, zmm, imm8, {sae} EVEX.512 -mavx512fp16

_mm512_maskz_roundscale_ph __m512h _mm512_maskz_roundscale_ph(__mmask32 A, __m512h B, const int imm)

VRNDSCALEPH zmm {k}{z}, zmm, imm8 EVEX.512 -mavx512fp16

_mm512_maskz_roundscale_round_ph __m512h _mm512_maskz_roundscale_round_ph(__mmask32 A, __m512h B, const int imm, const int R)

VRNDSCALEPH zmm {k}{z}, zmm, imm8, {sae} EVEX.512 -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_FP16_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16 + AVX512VL
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_FP16_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.