VRNDSCALEPS

VRNDSCALEPS rounds each single to a multiple of 2^-M, where M is bits 7:4 of the immediate, from 0 to 15. With M = 0 it rounds to an integral value, as VROUNDPS does, and its low four immediate bits mean what ROUNDPS’s do: bits 1:0 pick the direction (to nearest even, down, up, toward zero), bit 2 takes MXCSR’s rounding mode instead, and bit 3 suppresses the precision exception. It is AVX-512’s rounding instruction: VROUNDPS has no zmm form, no write mask and no access to xmm16 to xmm31.

Immediates in practice#

The intrinsic _mm512_floor_ps uses 01h, which does report an inexact result. With M above 0 the result keeps M fraction bits: in a case recorded on Zen 5, the immediate 10h, one bit to nearest, turned 0.431048 into 0.5. Values of 2^(23-M) and more are already multiples and come back unchanged, as do infinities; NaNs come back quiet.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 vectorizes a loop of nearbyintf into VRNDSCALEPS with 0Ch on zmm registers; a loop of floorf it vectorizes only with -ffast-math, with 09h, and otherwise rounds one element at a time with VRNDSCALESS. Clang 23 vectorizes both, with VEX VROUNDPS on ymm registers for -march=x86-64-v4 and VRNDSCALEPS on zmm for -march=znver5. Clang also turns the intrinsic _mm256_roundscale_ps(x, 1) into the shorter VROUNDPS, keeping VRNDSCALEPS where M is above 0.

Table indices#

Intel’s optimization manual uses the fraction bits for table-driven math functions (Section 17.15.3): to reduce x in [1, 2) for a logarithm, it rounds the estimate of 1/x from VRCP14PS to a few fraction bits with VRNDSCALE, takes the logarithm of that rounded value from a table and leaves only a small remainder for a polynomial.

AMD’s Zen 5 guide lists VRNDSCALEPS as one macro-op with a latency of 3 cycles, the same as VROUNDPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = src2.f32[i]
        zmm1.f32[i] = rndscale(a, imm8)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# m32bcst: src2.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALEPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPXORD
• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4

All 686 AVX10.1 instructions