VRNDSCALESD

VRNDSCALESD rounds the low double of its second source to a multiple of 2^-M, M being bits 7:4 of the immediate, and copies bits 127:64 from the first source. It is the scalar form of VRNDSCALEPD, and VRNDSCALEPS has the immediate’s table: with M = 0 it rounds to an integral value as VROUNDSD does, bits 1:0 choose the direction, bit 2 takes MXCSR’s mode instead and bit 3 suppresses the precision exception. The EVEX encoding adds a write mask on the one element, {sae} and xmm16 to xmm31, and clears the register from bit 128 up. VRNDSCALESS is the single-precision form.

Recorded on Zen 5#

• Nothing to round. vrndscalesd xmm7{k3}, xmm12, xmm7, {sae}, 0x11, rounding down to a multiple of 0.5, returned 7E37E43C8800759Ch, a double near 10^300 and so already an integer, unchanged, with bits 127:64 from XMM12 and MXCSR as it was.
• A signed zero. With the immediate F3h, truncation to 15 fraction bits, -0.0 from memory stayed -0.0 under zeroing with bit 0 of K7 set.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 compiles floor, trunc and nearbyint on a double to VRNDSCALESD with the immediates 09h, 0Bh and 0Ch, and round too with -ffast-math, after adding a constant just below 0.5 with the sign of the input. A floor loop over an array stays scalar, one VRNDSCALESD per element, unless -ffast-math lets GCC use VRNDSCALEPD on ZMM registers. Clang 23 uses VEX VROUNDSD for the same functions and VROUNDPD on YMM registers for the loop. Both compile _mm_roundscale_sd(a, b, 0x13), one fraction bit, to VRNDSCALESD; with 01h Clang switches to VROUNDSD and GCC keeps VRNDSCALESD.

AMD’s Zen 5 latency spreadsheet gives one macro-op, 3 cycles, two per cycle on pipes FP2 and FP3, as for VRNDSCALESS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = src3.f64[0]
    xmm1.f64[0] = rndscale(a, imm8)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALESD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPXORQ
• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2

All 686 AVX10.1 instructions