VRNDSCALESH

VRNDSCALESH rounds the low half of its second source to a multiple of 2^-M, M being bits 7:4 of the immediate, and copies bits 127:16 from the first source, clearing the bits above 127. It is the scalar form of VRNDSCALEPH, whose page covers the range of halves and the underflow that only FP16 can show, and the immediate is that of VRNDSCALEPS, with its table of the values C’s rounding functions use. Like VRNDSCALESS it takes a write mask on the one element, {sae} and xmm16 to xmm31, and reads two bytes when its source is in memory. The opcode is 0Ah in the 0F3A map with no prefix, where VRNDSCALESS has 66. VADDPH covers the format and the CPUID bits.

Every rounding function in one instruction#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile the _Float16 forms of floor, ceil, trunc, rint and roundeven to one VRNDSCALESH with the same register three times, as vrndscalesh xmm0, xmm0, xmm0, 9. The immediates are 09h, 0Ah, 0Bh, 04h and 08h: the last rounds to nearest even with the precision exception suppressed, while rint’s 04h reports an inexact result. A nearbyint, written as (_Float16)nearbyintf((float)x), gets 0Ch in both.

Narrowing a single-precision rounding is where they differ: (_Float16)floorf((float)x) becomes VRNDSCALESH in Clang, while GCC widens with VCVTSH2SS, rounds with VRNDSCALESS and narrows with VCVTSS2SH, unless -ffast-math lets it use VRNDSCALESH too. GCC also takes VRNDSCALESH, one element at a time, for loops of floor, ceil and trunc over halves that it vectorizes only with -ffast-math. _mm_roundscale_sh(a, b, 0x13) gives vrndscalesh xmm0, xmm0, xmm1, 19 in both.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRNDSCALESH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = src3.f16[0]
    xmm1.f16[0] = rndscale(a, imm8)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALESH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRANGEPD
• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4

All 686 AVX10.1 instructions