VRNDSCALESS

VRNDSCALESS rounds the low single of its second source to a multiple of 2^-M, M being bits 7:4 of the immediate, and copies bits 127:32 from the first source. It is the scalar form of VRNDSCALEPS, whose page has the immediate’s table: with M = 0 it rounds to an integral value as VROUNDSS does, bits 1:0 choose the direction, bit 2 takes MXCSR’s mode instead and bit 3 suppresses the precision exception. The EVEX encoding adds a write mask on the one element, {sae} and xmm16 to xmm31. VRNDSCALESD is the double-precision form.

Recorded on Zen 5#

• Masked off. vrndscaless xmm14{k1}, xmm8, xmm29, {sae}, 0x3, with bit 0 of K1 clear, kept the low single of XMM14 and still took bits 127:32 from XMM8; bits 511:128 were cleared.
• Infinity. With the immediate 04h, MXCSR’s mode, minus infinity from memory came back unchanged, and MXCSR kept its flags.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 compiles floorf, truncf and nearbyintf on a float to VRNDSCALESS with the immediates 09h, 0Bh and 0Ch, the same register three times, and uses it for each element of a floorf loop it does not vectorize. Clang 23 uses VEX VROUNDSS for the same functions and vectorizes the loop with VROUNDPS on YMM registers. Both compile _mm_roundscale_ss(a, b, 0x13), one fraction bit, to VRNDSCALESS; with 01h, which needs no fraction bit, Clang switches to VROUNDSS and GCC keeps VRNDSCALESS.

AMD’s Zen 5 latency spreadsheet gives one macro-op, 3 cycles, two per cycle on pipes FP2 and FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = src3.f32[0]
    xmm1.f32[0] = rndscale(a, imm8)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# imm8[7:4]: fraction bits kept; [1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRNDSCALESS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRANGEPS
• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2

All 686 AVX10.1 instructions