VROUNDPD

VROUNDPD rounds each double to a whole number, two to an xmm register and four to a ymm one, in the direction its immediate picks. It is the double-precision twin of VROUNDPS, whose page explains the immediate’s four bits and why AVX-512 code uses VRNDSCALEPD instead, there being no EVEX form; ROUNDPD is the SSE4.1 form that keeps the upper bits of its register. A double of magnitude 2^52 or more is already a whole number and comes back unchanged.

Edges recorded on Zen 5#

• Immediate 9 (down, precision exception suppressed), with DAZ set: the denormal -1.1 × 10^-308 became -0, not -1, as DAZ made it a zero before rounding; the smallest normal double, 2^-1022, became +0.
• Immediate 6, whose bit 2 defers to MXCSR, here rounding toward zero: the smallest and the largest denormal became +0, setting PE since bit 3 was clear, and a signaling NaN came back quiet with IE set.
• Immediate 3 (toward zero): -0 stayed -0 and infinity stayed infinity.

Rounding half away from zero#

C’s round rounds halves away from zero, a direction the immediate does not offer. Compilers build it from truncation: in our builds at -O2 for -march=x86-64-v3, GCC 14 (with -fno-trapping-math) and Clang 23 give 0.49999999999999994, the double just below 0.5, the sign of x, add it to x and truncate with VROUNDPD, immediate 3 or 11. With 0.5 itself, x = 0.49999999999999994 would fail: x + 0.5 rounds up to 1 in the addition, and truncation would keep the 1. For -march=x86-64-v4, the sign is merged with one VPTERNLOGQ instead of an AND and an OR.

floor, ceil, trunc and nearbyint map to single immediates, 9, 10, 11 and 12: Clang vectorizes floor over doubles to VROUNDPD on ymm registers for x86-64-v3 and x86-64-v4, and to VRNDSCALEPD on zmm for znver5; GCC 14 does so only with -fno-trapping-math, using VRNDSCALEPD on zmm for x86-64-v4.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    ymm1.f64[i] = round(src2.f64[i], imm8)
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VROUNDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSUBB
• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS

All 253 AVX instructions