VROUNDPS

VROUNDPS is the VEX form of ROUNDPS, whose page explains the immediate: bits 1:0 pick the direction, bit 2 hands it to MXCSR.RC instead, bit 3 keeps the precision exception quiet, and the C library’s floorf, ceilf, truncf and rintf each map to one value. The VEX form adds a separate destination, 256 bits, memory operands at any alignment and clearing of the bits above the result.

Bit 2 at work#

The cases recorded on Zen 5 show the immediate’s bits on halves, where the directions differ most:

• 2 (up) gave 1, -0, 2, 3 and -2 for 0.5, -0.5, 1.5, 2.5 and -2.5;
• 8 (to nearest, inexact suppressed) gave 2, 2 and -2 for 1.5, 2.5 and -2.5, ties going to the even neighbour;
• 0Dh asks for rounding down in bits 1:0, but its bit 2 defers to MXCSR, which was set to round toward zero: -2.5 became -2, not -3, and 0.5 became 0.

No EVEX form#

AVX-512 did not give VROUNDPS an EVEX encoding; it rounds with VRNDSCALEPS, whose immediate has the same low four bits and whose upper four bits, when zero, round to a whole number just as VROUNDPS does. So a compiler that targets AVX-512 picks by register: Clang 23 at -O2 vectorizes a loop over floorf to VROUNDPS with immediate 9 on ymm registers for -march=x86-64-v3 and also for x86-64-v4, where it works on ymm, and to VRNDSCALEPS on zmm registers for znver5. GCC 14 keeps that loop scalar unless -fno-trapping-math is given; with it, it emits VROUNDPS on ymm registers for x86-64-v3 and VRNDSCALEPS on zmm for x86-64-v4. Being VEX-only, VROUNDPS cannot reach registers 16 to 31 either.

AMD’s Zen 5 guide lists VROUNDPS, and VRNDSCALEPS at every width, as one macro-op with a latency of 3 cycles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    ymm1.f32[i] = round(src2.f32[i], imm8)
# imm8[1:0]: rn, rd, ru, rz; bit 2: MXCSR.RC; bit 3: no PE
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VROUNDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSUBD
• VPSUBQ
• VPSUBSB
• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD

All 253 AVX instructions