VRSQRT14PD

VRSQRT14PD estimates 1/sqrt(x) for each double within a relative error of 2^-14. It is the double form of VRSQRT14PS, whose page covers the special inputs and the Newton-Raphson step that refines an estimate. The older VRSQRTPS has no double form, so before AVX-512 a reciprocal root of doubles took VSQRTPD and VDIVPD.

Recorded on Zen 5#

• Few significant bits. All 17 positive finite results recorded end in 32 zero bits, and 2.0 and 0.5 gave 0.70706939697265625 and 1.4141387939453125, the very values VRSQRT14PS returns for them. The worst error, 0.866 times 2^-14, is at odd powers of two; even ones are exact: 4.0 gave 0.5 and 2^-1022 gave 2^511.
• Denormals. Without DAZ a denormal is a number: the smallest, 2^-1074, gave exactly 2^537. Under DAZ every denormal gave an infinity of its sign, -infinity for 8008000000000000h. The largest double gave 2^-512, so no result comes near the denormal range and FTZ has nothing to flush.
• No exceptions. With MXCSR 0, which unmasks them all, -1.0 gave the indefinite NaN FFF8000000000000h and a signaling NaN came back quiet, with no fault and no flag set.

Doubles in compiled code#

Intel’s optimization manual (Table 17-12) recommends VRSQRT14PD alone for 14 bits, with one Newton-Raphson iteration for 26 and two and an error correction for 52, against VSQRTPD and VDIVPD for the IEEE result; its Table 17-16 gives the bare instruction a latency of 4 cycles at 256 bits and 6 at 512 on Skylake. Compilers do not take that route: GCC 14 and Clang 23 at -O2 with -ffast-math, for -march=x86-64-v4 or -march=znver5, compile 1.0 / sqrt(a[i]) over double arrays to VSQRTPD and VDIVPD, where for floats Clang uses VRSQRT14PS with -march=znver5. VRSQRT14PD comes from _mm512_rsqrt14_pd and its 128- and 256-bit forms.

AMD’s Zen 5 latency spreadsheet gives VRSQRT14PD 5 cycles and two per cycle on pipes FP1 and FP2, as VRSQRT14PS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.f64[i] = rsqrt14(src2.f64[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# rsqrt14: 1/sqrt(a) within 2^-14; Zen 5's 17
# recorded results: 0.8663 * 2^-14 at most
# denormals by MXCSR.DAZ; a < 0: the indefinite; no flags
# m64bcst: src2.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRT14PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRANGESD
• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD

All 686 AVX10.1 instructions