VRSQRT14PS

VRSQRT14PS estimates 1/sqrt(x) for each single within a relative error of 2^-14, the square-root companion of VRCP14PS, whose page explains what such a bound means and why the bits differ between processors. The worst of the 52 results recorded on Zen 5 for this page is 0.8663 times 2^-14; the older VRSQRTPS is bound only to 1.5 times 2^-12. Even powers of two come back exact: Zen 5 gave 1.0 for 1.0 and 0.5 for 4.0, and 0.707069 for 2.0, where the true value is 0.707107. VRSQRT14PD is the double version, which the older instruction never had.

Special inputs#

+0 gives +infinity and -0 gives -infinity, keeping the sign; +infinity gives +0; any other negative input, -infinity included, gives the indefinite NaN FFC00000h. No MXCSR flag is ever set, not even for a signaling NaN, which comes back quiet. A denormal input counts as a zero only under DAZ; otherwise it has a large but finite reciprocal root, 2^63 for the largest denormal on Zen 5. The results never fall below the normal range, so FTZ does not apply.

Newton-Raphson and compilers#

One step, r’ = r(3 - xr^2)/2, roughly doubles the correct bits. Intel’s optimization manual recommends VRSQRT14PS alone for 14 bits, VRSQRT14PS and one step for 23 bits, and the same times x for a square root (Section 17.25.1, Table 17-11).

Compilers use it only under -ffast-math. For 1.0f / sqrtf(x), Clang 23 at -O2 with -march=znver5 emits VRSQRT14PS on zmm registers and one Newton step with VFMADD213PS and multiplications; with -march=x86-64-v4 it uses VRSQRTPS on ymm registers. GCC 14 vectorizes only at -O3, with VRSQRT14PS, and also replaces sqrtf(x) by x times the estimate: a compare with zero masks the estimate with {z}, so that x = 0 gives 0 rather than 0 times infinity, a NaN. Such results can differ in their last bit between processors, where VSQRTPS is always correctly rounded.

AMD’s Zen 5 guide lists VRSQRT14PS as one macro-op with a latency of 5 cycles, against 4 for VRSQRTPS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.f32[i] = rsqrt14(src2.f32[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# rsqrt14: 1/sqrt(a) within 2^-14; Zen 5's 52
# recorded results: 0.8663 * 2^-14 at most
# denormals by MXCSR.DAZ; a < 0: the indefinite; no flags
# m32bcst: src2.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRT14PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRANGESS
• VRCP14PD
• VRCP14PS
• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS

All 686 AVX10.1 instructions