VRSQRT14SS instruction (AVX10.1)

VRSQRT14SS estimates 1/sqrt(x) for the low single of its second source, within a relative error of 2^-14, and copies bits 127:32 from the first source. It is the scalar form of VRSQRT14PS, whose page covers the special inputs and the Newton-Raphson step, and the AVX-512 successor of VRSQRTSS, bound only to 1.5 times 2^-12. The EVEX encoding adds a write mask on the one element and xmm16 to xmm31, and clears the register from bit 128 up. No MXCSR flag is ever set. VRSQRT14SD is the double form.

Recorded on Zen 5

Denormals. Without DAZ, 00010802h gave 60B23E00h, 0.98 times 2^-14 below the true value, and the smallest denormal, 2^-149, gave 64B50280h, about 2^74.5. Under DAZ the largest denormal gave +infinity.
The top of the range. 2^127 gave 1FB50280h, about 2^-63.5, the same significand as for 2^-149: odd powers of two share one estimate of the square root of 2.
An SNaN. With MXCSR 0, 7F812345h came back as 7FC12345h, without a fault or a flag.
Masked off. With bit 0 of K5 clear, the merge kept the destination’s low single.

In compiled code

At -O2 with -march=x86-64-v4 and -ffast-math, GCC 14 and Clang 23 compile 1.0f / sqrtf(x) to the older VRSQRTSS and a Newton-Raphson step with one FMA, not to VRSQRT14SS. The instruction comes from _mm_rsqrt14_ss(a, b) and its masked forms.

AMD’s Zen 5 latency spreadsheet gives one macro-op and 5 cycles, two per cycle on pipes FP1 and FP2.

Forms

Every encoding of VRSQRT14SS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRSQRT14SS xmm {k}{z}, xmm, xmm` VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512	`EVEX.LIG.66.0F38.W0 4F /r`	AVX10.1 or AVX512F
`VRSQRT14SS xmm {k}{z}, xmm, m32` VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512	`EVEX.LIG.66.0F38.W0 4F /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm`	`xmm {k}{z}, xmm, m32`
Skylake-SP, Ice Lake	4 / 1p0	9 / 1p0
Sapphire Rapids	4 / 1p0	11 / 1p0
Zen 4	4 / 1FP1	11 / 1FP1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm2.

The write mask k1 applies to the low single: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result single 0 is computed from single 0 of xmm3; singles 3 to 1 are those of xmm2. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f32[0] = rsqrt14(src3.f32[0])
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# rsqrt14: 1/sqrt(a) within 2^-14; Zen 5's 4
# recorded results: 0.9830 * 2^-14 at most
# denormals by MXCSR.DAZ; a < 0: the indefinite; no flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 7 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRSQRT14SS xmm {k}{z}, xmm, xmm/m32`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRT14SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rsqrt14_ss` `__m128 _mm_rsqrt14_ss(__m128 __A, __m128 __B)`	`VRSQRT14SS xmm, xmm, xmm` EVEX.LIG -mavx512f
`_mm_mask_rsqrt14_ss` `__m128 _mm_mask_rsqrt14_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B)`	`VRSQRT14SS xmm {k}, xmm, xmm` EVEX.LIG -mavx512f
`_mm_maskz_rsqrt14_ss` `__m128 _mm_maskz_rsqrt14_ss(__mmask8 __U, __m128 __A, __m128 __B)`	`VRSQRT14SS xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Recorded on Zen 5#

In compiled code#