VRSQRT28SD instruction (AVX512ER)

Forms

Every encoding of VRSQRT28SD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRSQRT28SD xmm {k}{z}, xmm, xmm, {sae}` VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER	`EVEX.LIG.66.0F38.W1 CD /r`	AVX512ER
`VRSQRT28SD xmm {k}{z}, xmm, m64` VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER	`EVEX.LIG.66.0F38.W1 CD /r`	AVX512ER

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm2.

The write mask k1 applies to the low double: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result double 0 is computed from double 0 of xmm3; double 1 is that of xmm2. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 0)[1] >> 27 & 1:
    fault(UD)                    # CPUID: no AVX512ER
if k1[0]:
    xmm1.f64[0] = rsqrt28(src3.f64[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# rsqrt28: 1/sqrt(a) within 2^-28, rounded to a double
# denormals are zeros, whatever MXCSR says; a < 0: the
# indefinite; IE for an SNaN or a < 0, ZE for a zero
# {sae}: no exception flags
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no AVX512ER, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRSQRT28SD xmm {k}{z}, xmm, xmm/m64, {sae}`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: write masking; follows MXCSR
Memory forms: memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX512ER_SCALAR` AVX512ER	AVX512ER `CPUID.(EAX=07H,ECX=0):EBX[27]` AVX512ER	Knights Landing, Knights Mill

VRSQRT28SD