VRSQRTBF16

VRSQRTBF16 estimates 1/sqrt(x) for each bfloat16 value, 8, 16 or 32 per register, with a relative error below 2^-8 + 2^-14, the bound of VRCPBF16, whose page explains why that is close to the correctly rounded result for a bfloat16. It belongs to AVX10.2; the opcode is 4Eh in EVEX map 6 with no prefix and W0, where VRSQRTPH has 66, and the source may be broadcast from 16 bits of memory.

Special inputs#

The AVX10.2 specification (revision 7.0) gives +infinity for +0 and -infinity for -0, +0 for +infinity, the default NaN for every negative input, -infinity included, and exact powers of two for even powers of two. Denormals are read as zeros, so a positive denormal gives +infinity. The table lists a negative denormal under two rows, the -infinity row marked DAZ and the NaN row for every x below 0; read as -0, as DAZ requires, it gives -infinity. Like VRCPBF16’s entry, this one lacks the sentence on exceptions and MXCSR that VADDBF16’s entry has, and relies on exception class E4, defined in Section 4.2.5 as causing no SIMD floating-point exceptions.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 at -O2 with -mavx10.2 compiles _mm512_rsqrt_pbh to VRSQRTBF16. A loop of 1 / __builtin_elementwise_sqrt(X[i]) over global __bf16 arrays stays VSQRTBF16 and VDIVBF16, even with -ffast-math, unlike the FP16 loops on VRSQRTPH’s page. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.bf16[i] = rsqrt(src2.bf16[i])
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# rsqrt: 1/sqrt(a) within 2^-8 + 2^-14
# a < 0: the indefinite
# BF16: denormals flushed, in and out, no flags; MXCSR unused
# m16bcst: src2.bf16[i] is the m16 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRTBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16
• VUCOMXSD
• VUCOMXSH
• VUCOMXSS

All 96 AVX10.2 instructions