VRSQRTPH

VRSQRTPH estimates 1/sqrt(x) for each half, 32 per zmm register, with a relative error below 2^-11 + 2^-14, the bound of VRCPPH, whose page explains why that is close to the correctly rounded result for a half. The opcode is 4Eh in EVEX map 6 with the 66 prefix, VRSQRT14PS’s byte in 0F38; there is no rounding mode, no MXCSR flag and no SIMD exception. VRSQRT14PS is the single-precision form, which needs a Newton-Raphson step, and VADDPH covers the format and the CPUID bits.

Special inputs#

Intel’s table gives +infinity for +0 and -infinity for -0, +0 for +infinity, and the default NaN for every negative input, -infinity included; exact even powers of two map to exact powers of two. Every denormal gives a normal result: even the smallest, 2^-24, has the reciprocal square root 2^12, so nothing overflows, and FP16 instructions ignore DAZ, so a denormal is never read as zero.

Better than the exact sequence#

Intel’s optimization manual finds VRSQRTPH within 0.5 ULP for 98% of inputs and 0.5625 ULP for the rest, which is closer than dividing 1 by the correctly rounded square root, where two roundings stack up (Section 18.5.8.3). It takes 6 cycles at 512 bits against 48 for that sequence. Multiplied by x, it gives a square root that matches VSQRTPH for 70% of inputs and is never more than 1 ULP off (Section 18.5.9).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16 and -ffast-math, GCC 14 and Clang 23 compile 1 / sqrtf16(a[i]) over a _Float16 array to VRSQRTPH alone, with no refinement step, and sqrtf16(a[i]) to VSQRTPH, not to the product. Without -ffast-math, where a negative input must set errno, GCC computes VSQRTSH per element and calls sqrtf16 only when the result is a NaN, while Clang calls it for every element. The intrinsic _mm512_rsqrt_ph gives VRSQRTPH in both. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRSQRTPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = rsqrt(src2.f16[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# rsqrt: 1/sqrt(a) within 2^-11 + 2^-14; denormals kept;
# a < 0: the indefinite; no flags
# m16bcst: src2.f16[i] is the m16 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRTPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRCP14SD
• VRCP14SS
• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS

All 686 AVX10.1 instructions