VRSQRTPS

VRSQRTPS estimates 1/sqrt(x) for each single, the VEX form of the legacy RSQRTPS with a 256-bit form added. Both vendors’ manuals promise only a relative error of at most 1.5 times 2^-12, about 11 correct bits, and not which bits: the result can differ between processors. On Zen 5 the estimate for 1 was 0.99987793, not 1, for 4 it was 0.499938965 and for 2 it was 0.70703125, where the true value is 0.70710678. MXCSR’s rounding control plays no part, and no MXCSR flag is ever set.

Special inputs#

Intel’s and AMD’s manuals agree, and the cases recorded on Zen 5 for VRSQRTPS and RSQRTPS match:

• +0 gives +infinity and -0 gives -infinity;
• a denormal counts as a zero of its sign even with DAZ clear: the smallest denormal gave +infinity, and a negative one -infinity;
• +infinity gives +0, and any other negative input, -infinity included, the indefinite NaN FFC00000h;
• a NaN comes back quiet, without IE even when every exception is unmasked.

Refining the estimate#

One Newton-Raphson step, r(3 - x r^2) / 2, brings it to about 22 bits. Intel’s optimization manual recommends the estimate alone where 11 bits are enough and one step where 22 are, and found on Skylake that for 1/sqrt(x) on 256-bit vectors the two run at 7.7 and 3 times the throughput of VSQRTPS followed by VDIVPS (Section 15.12, Tables 15-5 and 15-6).

Compilers use it only under -ffast-math. Then GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 compile 1.0f / sqrtf(x) over floats to VRSQRTPS and one Newton-Raphson step with an FMA. For -march=x86-64-v4, Clang keeps VRSQRTPS on ymm registers, while GCC switches to VRSQRT14PS on zmm registers.

There is no EVEX form: AVX-512 has VRSQRT14PS instead, accurate to 2^-14, and that page compares the two on Zen 5.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    ymm1.f32[i] = rsqrt(src2.f32[i])
# rsqrt: 1/sqrt(a) within 1.5 * 2^-12; Zen 5's 7
# recorded results: 0.5000 * 2^-12 at most
# a denormal is a zero, whatever MXCSR says; a < 0: the
# indefinite; no flags
# ymm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSUBSW
• VPSUBUSB
• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS

All 253 AVX instructions