VRSQRTSH instruction (AVX10.1)

VRSQRTSH estimates 1/sqrt(x) for the low half of its second source, with a relative error below 2^-11 + 2^-14, and copies bits 127:16 from the first source, clearing the bits above 127. It is the scalar form of VRSQRTPH, whose page covers the special inputs (infinity for a zero of the same sign, the default NaN for any negative input, a normal result for every denormal) and Intel’s measurement of its accuracy. The encoding is 4Fh with the 66 prefix in EVEX map 6, with a write mask on the low half and a two-byte memory operand; there is no rounding mode and no SIMD exception. VADDPH covers the format and the CPUID bits, and VRCPSH estimates a reciprocal.

Better than dividing

Intel’s optimization manual finds the estimate within 0.5 ULP of the true value for 98% of inputs and within 0.5625 ULP for the rest, which is closer than one divided by a correctly rounded square root, where two roundings add up (Section 18.5.8.3). Unlike VRCPSH, both compilers use it for that expression. At -O2 with -march=x86-64-v4 -mavx512fp16 and -ffast-math, GCC 14 and Clang 23 compile 1 / sqrtf16(x) on a _Float16 value to vrsqrtsh xmm0, xmm0, xmm0 alone, and y / sqrtf16(x) to VRSQRTSH and a VMULSH; with only -fno-math-errno both keep VSQRTSH and VDIVSH. A plain sqrtf16(x) stays VSQRTSH either way, not x times the estimate, the cheaper product that matches the square root for 70% of inputs (Section 18.5.9).

_mm_rsqrt_sh(a, b) gives vrsqrtsh xmm0, xmm0, xmm1, and the masked _mm_mask_rsqrt_sh a merge-masked VRSQRTSH, in both compilers.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VRSQRTSH.

Forms

Every encoding of VRSQRTSH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VRSQRTSH xmm {k}{z}, xmm, xmm` VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512	`EVEX.LIG.66.MAP6.W0 4F /r`	AVX10.1 or AVX512_FP16
`VRSQRTSH xmm {k}{z}, xmm, m16` VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512	`EVEX.LIG.66.MAP6.W0 4F /r`	AVX10.1 or AVX512_FP16

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm {k}{z}, xmm, xmm`	`xmm {k}{z}, xmm, m16`
Sapphire Rapids	4 / 1p0	11 / 1p0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low half is computed; the other halves come from xmm2.

The write mask k1 applies to the low half: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result half 0 is computed from half 0 of xmm3; halves 7 to 1 are those of xmm2. Result halves 7 to 0: a7, a6, a5, a4, a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.f16[0] = rsqrt(src3.f16[0])
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# rsqrt: 1/sqrt(a) within 2^-11 + 2^-14; denormals kept;
# a < 0: the indefinite; no flags
# xmm1 is zeroed from bit 128 up

Not run on a processor: none of these processors has AVX512-FP16.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VRSQRTSH xmm {k}{z}, xmm, xmm/m16`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E10

Attributes

What else XED records about the forms. How to read.

All forms: write masking
Memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VRSQRTSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_rsqrt_sh` `__m128h _mm_rsqrt_sh(__m128h __A, __m128h __B)`	`VRSQRTSH xmm, xmm, xmm` EVEX.LIG -mavx512fp16
`_mm_mask_rsqrt_sh` `__m128h _mm_mask_rsqrt_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B)`	`VRSQRTSH xmm {k}, xmm, xmm` EVEX.LIG -mavx512fp16
`_mm_maskz_rsqrt_sh` `__m128h _mm_maskz_rsqrt_sh(__mmask8 __U, __m128h __A, __m128h __B)`	`VRSQRTSH xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512fp16

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_FP16_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

More AVX10.1 instructions

All 686 AVX10.1 instructions

Better than dividing#