VSCALEFPD

VSCALEFPD multiplies each double of the first source by 2 to the power of the matching double of the second, rounded down to an integer first: a times 2^floor(b), with a single rounding of the result. VSCALEFPS describes the operation for singles: the floor, the infinite scales that follow the limits, the quiet NaN scaled by an infinity, and its use with VGETEXP and VREDUCE for exponentials. With doubles the scale reaches further: a result can run from the smallest denormal, 2^-1074, to the largest finite double near 2^1024 before it underflows to zero or overflows to infinity.

Recorded on Zen 5#

The cases recorded on Zen 5 show the floor on both sides of zero:

• 1.0 scaled by -2.5 gave 0.125, and -3.0 scaled by -0.5 gave -1.5, since the floor of -0.5 is -1; 3.0 scaled by 0.5 stayed 3.0.
• With a broadcast scale of -infinity, 1.0 became +0.0 and -0.0 stayed -0.0, while a signaling NaN in the first source came back quiet, 7FF8000000012345h, and set MXCSR’s IE flag.
• +infinity and -infinity scaled by -infinity gave the default NaN FFF8000000000000h with IE, while +infinity scaled by +infinity stayed +infinity.
• Under {rn-sae}, a quiet NaN scale was passed through and a signaling NaN source quieted, without a flag.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -ffast-math compile ldexp(a, e) to the scalar VSCALEFSD after converting e to a double, and a loop of ldexp over arrays stays scalar, one VSCALEFSD per element. GCC also compiles scalbn that way, where Clang calls the library. VSCALEFPD itself comes from _mm512_scalef_pd and its kin.

AMD’s latency spreadsheet for Zen 5 lists VSCALEFPD as VSCALEFPS: two macro-ops on FP2 and FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = scalef(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRCPPH
• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH

All 686 AVX10.1 instructions