VSCALEFPH

VSCALEFPH multiplies each half of its first source by 2 raised to the floor of the matching half of the second, a × 2^floor(b), and rounds once, by MXCSR.RC or by {er} on the 512-bit register form. It is VSCALEFPS for halves, and that page explains the floor, the limits for infinite scales and the surprises of the special case table, which the FP16 entry repeats; its opcode is 2Ch in EVEX map 6 with the 66 prefix, VSCALEFPS’s byte in 0F38. VADDPH covers the format and the CPUID bits, and VGETEXPPH and VGETMANTPH the split that VSCALEFPH undoes.

Scales in a half#

Every scale that does anything fits a half exactly: integers up to 2048 are exact, and a result passes 65504 or falls below the smallest denormal, 2^-24, before a scale reaches ±40. A result out of range overflows to infinity or underflows to a denormal or zero with the usual flags, and since FP16 instructions ignore FTZ and DAZ (Intel’s optimization manual, Section 18.5.4), a denormal first source is scaled as the value it holds and a tiny result stays a denormal. Intel’s entry lists DE for a denormal first source only; a denormal scale is between -1 and 1 and is floored to 0 or -1.

Intel’s entry has a slip in its overflow row: it gives the largest denormal as the result when rounding keeps an overflow finite, where it means the largest normal half, 65504.

In our builds#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -mavx512fp16 emit VSCALEFPH for _mm512_scalef_ph. ldexpf on a _Float16 is a library call between VCVTSH2SS and VCVTSS2SH by default; with -ffast-math both compilers use the single-precision VSCALEFSS instead of the call, and Clang vectorizes a loop of it over a _Float16 array as VCVTPH2PSX, VCVTDQ2PS for the int exponents and VSCALEFPS, which it does not do for a float array. Neither uses VSCALEFPH for it. AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSCALEFPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = scalef(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src3.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRCPSH
• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS

All 686 AVX10.1 instructions