VSCALEFPS

VSCALEFPS multiplies each single of the first source by 2 to the power of the matching single of the second, rounded down to an integer first: a times 2^floor(b). Both operands are floating-point, unlike C’s ldexpf, whose exponent is an int, and the result is rounded once, so it overflows to infinity, underflows to a denormal or zero, and sets MXCSR’s flags as a multiplication would. The x87 counterpart FSCALE truncates its scale toward zero instead.

The floor and the special cases#

The floor applies to negative scales too: a scale of -2.5 multiplies by 1/8, not 1/4, and a negative denormal scale, which is above -1, still halves. Zen 5 recorded both: 1.0 scaled by -2.5 gave 0.125, and -1.0 scaled by -5.9e-39 gave -0.5. A positive denormal scale leaves the value alone.

Infinite scales follow the limits rather than NaN rules: a finite nonzero value scaled by +infinity becomes an infinity of its sign, and by -infinity a zero of its sign. A zero scaled by +infinity and an infinity scaled by -infinity are invalid and give the default NaN. The manuals’ table has one surprise: a quiet NaN scaled by +infinity gives +infinity, and by -infinity +0, where nearly every other operation passes the NaN on. Zen 5 recorded the same.

What it is for#

Intel’s optimization manual builds exponentials on it (Section 17.15.5): exp2(x) is 2 to the fractional part of x, computed with VREDUCEPS and a polynomial, scaled by x itself with VSCALEF, which takes the floor of x on its own and handles overflow, underflow and infinite inputs without a separate path. With VGETEXPPS and VGETMANTPS it also reassembles a number split into exponent and significand.

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 -ffast-math compile ldexpf(a, e) to the scalar VSCALEFSS after converting e to a single; without -ffast-math both call the library. Neither vectorizes a loop of ldexpf calls, but Clang turns the same loop written with __builtin_ldexpf, over float or _Float16 arrays, into VSCALEFPS on ymm registers, the exponents converted with VCVTDQ2PS; GCC keeps VSCALEFSS. Otherwise VSCALEFPS comes from the intrinsic _mm512_scalef_ps and its kin.

AMD’s Zen 5 guide lists VSCALEFPS as two macro-ops, where VGETEXPPS and VRNDSCALEPS are one.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = scalef(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCEPD
• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD

All 686 AVX10.1 instructions