VSCALEFSD

VSCALEFSD multiplies the low double of its first source by 2 to the power of the low double of its second source, rounded down to an integer first, a times 2^floor(b), with one rounding of the result, and copies bits 127:64 from the first source. It is the scalar form of VSCALEFPD, and VSCALEFPS describes the operation: the floor, the infinite scales, the NaNs and the use with VGETEXP in exponentials. The EVEX encoding adds a write mask on the one element, a rounding override {er} and xmm16 to xmm31, and clears the register from bit 128 up. Unlike VGETEXPSD, whose exponent it can put back, it can raise overflow, underflow and precision exceptions. VSCALEFSS is the single-precision form.

Recorded on Zen 5#

• An exact result. Under {rd-sae}, 2.5 scaled by -126 gave 3824000000000000h, exactly 2.5 times 2^-126, with MXCSR unchanged and bits 127:64 from the first source.
• Scale -infinity. Under zeroing with bit 0 of K2 set, -1.0 scaled by -infinity from memory gave -0.0.

In compiled code#

At -O2 with -march=x86-64-v4 -ffast-math, GCC 14 and Clang 23 compile ldexp(x, n) to VCVTSI2SD, which turns n into a double, and one VSCALEFSD, as VSCALEFPD’s page shows for loops; without -ffast-math both call ldexp. The intrinsic _mm_scalef_sd(a, b) is one VSCALEFSD in both.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP2 and FP3, one per cycle, with 6 cycles for a register second source and 3 listed for a memory one.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = scalef(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCEPH
• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH

All 686 AVX10.1 instructions