VSCALEFSH

VSCALEFSH multiplies the low half of its first source by 2 raised to the floor of the low half of the second, a × 2^floor(b), and rounds once, under MXCSR.RC or, between registers, under {er}. Bits 127:16 come from the first source and the bits above 127 are cleared. It is the scalar form of VSCALEFPH, whose page shows that every scale that matters fits a half and points out a slip in Intel’s table of special cases, and of which VSCALEFPS explains the floor and the results for infinite and NaN scales. The encoding is 2Dh with the 66 prefix in EVEX map 6, VSCALEFSS’s byte in 0F38, with a write mask on the low half and a two-byte memory operand. VADDPH covers the format and the CPUID bits.

Flags for one operand only#

Intel’s entry reports invalid, overflow, underflow, precision and denormal, the last for the first source only: a denormal scale is between -1 and 1 and only its floor matters, and a NaN scale gives a NaN without a denormal flag even when the first source is a denormal. Its description still names MXCSR’s FTZ bit among the settings that shape an underflow, but FP16 arithmetic ignores FTZ and DAZ (Intel’s optimization manual, Section 18.5.4), so a tiny result stays a denormal.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 emit vscalefsh xmm0, xmm0, xmm1 for _mm_scalef_sh(a, b). C’s ldexpf on a _Float16 value and an int exponent is a library call between VCVTSH2SS and VCVTSS2SH by default; with -ffast-math both compilers inline it, but in single precision: they convert the exponent with VCVTSI2SS and scale with VSCALEFSS, keeping the conversions around it. A multiplication by a constant power of two, such as x * 8, is a VMULSH with the constant from memory.

Intel’s optimization manual names VSCALEF for exponential and power functions, where its handling of overflow and underflow spares the main path a fix-up (Section 18.7).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSCALEFSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = scalef(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCEPS
• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS

All 686 AVX10.1 instructions