VSCALEFSS

VSCALEFSS multiplies the low single of its first source by 2 to the power of the low single of its second source, rounded down to an integer first, a times 2^floor(b), and copies bits 127:32 from the first source. It is the scalar form of VSCALEFPS, whose page describes the floor, the infinite scales, the NaNs and the use in exponentials. The EVEX encoding adds a write mask on the one element, a rounding override {er} and xmm16 to xmm31, and clears the register from bit 128 up. Under DAZ a denormal input counts as zero. VSCALEFSD is the double form.

Recorded on Zen 5#

• A denormal doubled. Under {rz-sae}, the smallest denormal, 00000001h, scaled by 1.0 gave 00000002h. MXCSR had DM, UM and PM unmasked, but the override suppresses exceptions, so the denormal input and the tiny result raised no fault and set no flag.
• DAZ. With DAZ and FTZ set, the same denormal scaled by 1.0 from memory counted as zero and gave +0.
• Upper bits. In both cases bits 127:32 came from the first source, 1.0, -1.0 and 1.0 here, and bits 511:128 were cleared.

In compiled code#

At -O2 with -march=x86-64-v4 -ffast-math, GCC 14 and Clang 23 compile ldexpf(x, n) to VCVTSI2SS and one VSCALEFSS; without -ffast-math both call ldexpf. The intrinsic _mm_scalef_ss(a, b) is one VSCALEFSS in both.

AMD’s Zen 5 latency spreadsheet gives two macro-ops on pipes FP2 and FP3, one per cycle, with 6 cycles for a register second source and 3 listed for a memory one, as for VSCALEFSD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = scalef(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCALEFSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCESD
• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD

All 686 AVX10.1 instructions