VSCATTERDPD

VSCATTERDPD stores doubles to scattered addresses: element i goes to a base plus element i of an index vector, a signed 32-bit integer, times a scale of 1, 2, 4 or 8. The indices are half as wide as the data, so eight doubles of a ZMM register take their indices from a YMM register, and the YMM and XMM forms take four and two from an XMM register. It is VPSCATTERDQ under a floating-point name: the bits are stored as they are, with no SIMD exception. VSCATTERDPS’s page and VPSCATTERDD’s explain what all scatters share: the mask cleared as elements are stored, repeated indices and the faults they can resume after. VSCATTERQPD takes 64-bit indices instead, and VGATHERDPD is the load it mirrors. It came with AVX512F.

Recorded on Zen 5#

• Three of eight. vscatterdpd qword ptr [base + ymm3*8]{k4}, zmm1, with 2Ch in the low byte of K4, stored elements 2, 3 and 5 at indices 3, 2 and -5, the last 40 bytes below the base, and nothing else.
• Four of four. The YMM form with indices -8, 0, 3 and 1 in XMM30 stored all four elements, the first one 64 bytes below the base.
• Nothing selected. In the XMM form, whose two mask bits were both clear, nothing was stored.
• Mask. K4 and K7 ended as 0 in every case, all 64 bits.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile dd[ix[i]] = ds[i] over doubles with int indices to VSCATTERDPD, GCC from ZMM registers with YMM indices, Clang from YMM registers with XMM indices, each scatter after a fresh all-ones mask. With -march=znver5 Clang moves to ZMM registers, while GCC keeps the loop scalar. Under a condition, if (ds[i] > 0), the mask of the VCMPPD becomes the scatter’s mask. For x86-64-v4, _mm512_i32scatter_pd is KXNORB and VSCATTERDPD in both compilers.

AMD’s Zen 5 latency spreadsheet lists VSCATTERDPD as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VSCATTERDPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        store(mem.base + a, 64, zmm2.q[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCATTERDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCESH
• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH

All 686 AVX10.1 instructions