VSCATTERDPS

VSCATTERDPS stores the singles of a vector to scattered addresses: element i goes to a base plus element i of a vector of signed 32-bit indices, times 1, 2, 4 or 8. It is the store that mirrors VGATHERDPS, and it works exactly as VPSCATTERDD, whose page covers the mask that is cleared as elements are stored, repeated indices and the cost of a scatter: the singles are moved as 32-bit patterns, so nothing is rounded and no MXCSR flag is raised. Like every scatter it exists only in AVX-512, and K0, which would mean no mask, is not allowed.

Signed indices#

The indices are sign-extended before the scaling, so they reach below the base as well as above it. In a case recorded on Zen 5, vscatterdps [base + zmm14*4]{k5}, zmm7 stored eleven of its 16 elements, those K5 selected, at indices from -15 to 14, element 14 with index -15 going to 60 bytes below the base; the other 21 dwords of the buffer kept their values, and K5 ended as zero. The XMM and YMM forms, which take 4 and 8 indices, did the same with their low mask bits.

In compiled code#

GCC 14 and Clang 23 at -O2 vectorize d[idx[i]] = s[i] over float for -march=x86-64-v4: GCC with ZMM registers and an all-ones mask from KXNORW, Clang with YMM registers and KXNORB. Clang also scatters where the addresses follow a constant stride: d[5*i] = s[i] became VSCATTERQPS with a vector of constant 64-bit offsets, while GCC kept that loop scalar.

Intel’s optimization manual uses VSCATTERDPS in its scatter example (Section 17.11.1): dst[ind[i]] = (float)src[i] with 64-bit integer sources, where the hardware version converts two ZMM registers with VCVTUQQ2PS, joins the halves with VSHUFF32X4 and stores the 16 results with one VSCATTERDPS under a mask made by KXNORW. With int64_t sources and -march=x86-64-v4, our builds of that loop scatter as well: GCC converts two ZMM registers with VCVTQQ2PS, joins them with VINSERTF32X8 and scatters 16 singles at once, much as Intel’s example does, while Clang converts and scatters four at a time in XMM registers.

In the optimization guide

What the optimization guide says about VSCATTERDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        store(mem.base + a, 32, zmm2.d[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCATTERDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VREDUCESS
• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS

All 686 AVX10.1 instructions