VSCATTERQPD

VSCATTERQPD stores doubles to scattered addresses, element i at a base plus element i of an index vector, a signed 64-bit integer, times a scale. It is VPSCATTERQQ under a floating-point name: the bits are stored as they are, with no SIMD exception, and the forms are the same, 8, 4 or 2 elements with as many indices. VSCATTERDPS’s page and VPSCATTERDD’s explain what all scatters share: the mask cleared as elements are stored, repeated indices and the faults they can resume after. It came with AVX512F.

Recorded on Zen 5#

• Three of eight. vscatterqpd qword ptr [base + zmm9*8]{k6}, zmm4, with C2h in the low byte of K6, stored elements 1, 6 and 7 at indices 3, -1 and -2, the last two below the base, and nothing else.
• Unaligned. With a scale of 1, the XMM form wrote its one selected element at byte 42 past the base, across two aligned quadwords.
• Mask. K6 and K5 ended as 0 in every case, all 64 bits.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile dd[ix[i]] = ds[i] over doubles with long indices to VSCATTERQPD, GCC from ZMM registers, Clang from YMM registers, and from ZMM ones with -march=znver5, where GCC keeps the loop scalar. With a condition, if (ds[i] > 0), the compare’s mask becomes the scatter’s mask, so no all-ones mask is needed. _mm512_mask_i64scatter_pd takes its mask from a general-purpose register with KMOVB in GCC and KMOVD in Clang.

AMD’s Zen 5 latency spreadsheet lists VSCATTERQPD as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VSCATTERQPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        store(mem.base + a, 64, zmm2.q[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCATTERQPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALEPD
• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD

All 686 AVX10.1 instructions