VSCATTERQPS

VSCATTERQPS stores singles to scattered addresses, element i at a base plus element i of an index vector, a signed 64-bit integer, times a scale. Here the data are half as wide as the indices: eight indices in a ZMM register place the eight singles of a YMM register, and the YMM and XMM index forms place four or two singles from an XMM register. It is VPSCATTERQD under a floating-point name, storing the bits as they are, and VSCATTERDPS’s page explains what all scatters share: the mask cleared as elements are stored, repeated indices and the faults they can resume after. VGATHERQPS is the load it mirrors, and VSCATTERQPD the same store of doubles. It came with AVX512F.

Recorded on Zen 5#

• Four of eight. vscatterqps dword ptr [base + zmm3*4]{k6}, ymm1, with 66h in the low byte of K6, stored elements 1, 2, 5 and 6 at indices -8, -1, 1 and -13: three below the base, one above.
• The YMM index form. With indices 15, -4, -2 and 4 and the third mask bit clear, three singles were stored, at 60 bytes above, 16 below and 16 above the base.
• Mask. K6, K3 and K5 ended as 0 in every case, all 64 bits, also when the XMM index form had no element selected and stored nothing.

In compiled code#

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 compile fd[lx[i]] = fs[i] over floats with long indices to VSCATTERQPS, GCC with ZMM indices and YMM data, Clang with YMM indices and XMM data; with -march=znver5, Clang moves to ZMM indices and GCC keeps the loop scalar. For x86-64-v4, _mm512_i64scatter_ps is KXNORB and VSCATTERQPS in both.

AMD’s Zen 5 latency spreadsheet lists VSCATTERQPS as microcoded, as every scatter.

In the optimization guide

What the optimization guide says about VSCATTERQPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Scatters store one element at a time; Intel replaces short-stride scatters by permutes and stores, and they are microcode on Zen 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        store(mem.base + a, 32, ymm2.d[i])
k1.write(0)  # all of it

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

scatter; write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCATTERQPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALEPH
• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH

All 686 AVX10.1 instructions