x86-64.net

Instruction

VSCATTERQPS

Stores singles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects.

Extensions
Forms
3 (3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VSCATTERQPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSCATTERQPS vm64z {k}, ymm VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512EVEX.512.66.0F38.W0 A3 /rAVX10.1 or AVX512F
VSCATTERQPS vm64x {k}, xmm VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128EVEX.128.66.0F38.W0 A3 /rAVX10.1 or AVX512F + AVX512VL
VSCATTERQPS vm64y {k}, xmm VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256EVEX.256.66.0F38.W0 A3 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSCATTERQPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_i64scatter_ps void _mm_i64scatter_ps(void *addr, __m128i index, __m128 v1, const int scale)

VSCATTERQPS vm64x {k}, xmm EVEX.128 -mavx512vl

_mm_mask_i64scatter_ps void _mm_mask_i64scatter_ps(void *addr, __mmask8 mask, __m128i index, __m128 v1, const int scale)

VSCATTERQPS vm64x {k}, xmm EVEX.128 -mavx512vl

_mm256_i64scatter_ps void _mm256_i64scatter_ps(void *addr, __m256i index, __m128 v1, const int scale)

VSCATTERQPS vm64y {k}, xmm EVEX.256 -mavx512vl

_mm256_mask_i64scatter_ps void _mm256_mask_i64scatter_ps(void *addr, __mmask8 mask, __m256i index, __m128 v1, const int scale)

VSCATTERQPS vm64y {k}, xmm EVEX.256 -mavx512vl

_mm512_i64scatter_ps void _mm512_i64scatter_ps(void *addr, __m512i index, __m256 v1, const int scale)

VSCATTERQPS vm64z {k}, ymm EVEX.512 -mavx512f

_mm512_mask_i64scatter_ps void _mm512_mask_i64scatter_ps(void *addr, __mmask8 mask, __m512i index, __m256 v1, const int scale)

VSCATTERQPS vm64z {k}, ymm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.