Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VSHA512MSG2 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSHA512MSG2 ymm, ymm VSHA512MSG2_YMMu64_YMMu64VEX.256.F2.0F38.W0 CD /rSHA512 + AVX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHA512MSG2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_sha512msg2_epi64 __m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B)

VSHA512MSG2 ymm, ymm VEX.256 -msha512

VSHA512MSG2 ymm, ymm VEX.256 -msha512 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SHA512

SHA512 + AVX
CPUID.(EAX=07H,ECX=1):EAX[0] SHA512
CPUID.01H:ECX[28] AVX

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

More SHA512 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.