Instruction
VSHA512MSG2
Completes the SHA-512 message schedule computation for the next four message quadwords.
- Extensions
- Forms
- 1 (1 VEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VSHA512MSG2 ymm, ymm
VSHA512MSG2_YMMu64_YMMu64 | VEX.256.F2.0F38.W0 CD /r | SHA512 + AVX |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VSHA512MSG2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_sha512msg2_epi64
__m256i _mm256_sha512msg2_epi64(__m256i __A, __m256i __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
SHA512 | SHA512 + AVX | Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest |
More SHA512 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.