VSHUFF32X4

VSHUFF32X4 is the floating-point name of VSHUFI32X4: it moves 128-bit blocks of singles with the immediate that VSHUFI64X2’s page explains, the low two blocks of the result from the first source and the high two from the second, and masks single by single. It moves bits without arithmetic, so nothing in MXCSR changes; all 4 cases recorded on Zen 5 left it at 1F80h.

Recorded on Zen 5#

• One register three times. vshuff32x4 zmm5{k6}, zmm5, zmm5, 0x74 built blocks 0 to 3 from blocks 0, 1, 3 and 1 of ZMM5. K6’s low 16 bits, 43A4h, let only singles 2, 5, 7 to 9 and 14 through, so singles 8 and 9 took block 3’s first two, single 14 block 1’s third, and the rest of ZMM5 kept its value.
• Broadcast. In vshuff32x4 zmm9{k3}, zmm9, dword bcst [mem], 0x20 the second source is one single repeated, so blocks 2 and 3, chosen from it, held that single wherever AAEBh, the low 16 bits of K3, had a bit set.
• At 256 bits only bits 1:0 count. With 11h, vshuff32x4 ymm1{k1}, ymm2, ymmword ptr [mem], 0x11 chose the high block of YMM2 for the low half and, bit 1 being clear, the low block of memory for the high half; A0h in K1 let only singles 5 and 7 of it through.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 treat the ps intrinsics as the integer ones: both keep VSHUFF32X4 for _mm512_mask_shuffle_f32x4 and its zero-masked form. Unmasked, GCC keeps it for _mm512_shuffle_f32x4 and for block moves of float vectors written with __builtin_shufflevector, while Clang emits VSHUFF64X2, VINSERTF64X4 when the result is the low halves of the two sources (0x44), and VPERM2F128 for the 256-bit form.

AMD’s Zen 5 latency spreadsheet gives VSHUFF32X4 3 cycles at 256 bits and 5 at 512, two per cycle on pipes FP1 and FP2, as VSHUFI32X4.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    lane = i // 4
    if VL == 256:
        x = imm8 >> lane & 1      # one bit per lane
    else:
        x = imm8 >> 2 * lane & 3  # two bits per lane
    j = x * 4 + i % 4
    if k1[i]:
        if lane < VL // 256:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFF32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALEPS
• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS

All 686 AVX10.1 instructions