VSHUFF64X2

VSHUFF64X2 builds a ZMM or YMM register from 128-bit blocks of two sources, each block chosen by a field of the immediate, and writes the result under a mask of doubles. It is VSHUFI64X2 under a floating-point name, and that page explains the immediate, the 256-bit form and what a mask of quadwords can do with half-blocks; VSHUFF32X4 moves the same blocks under a mask of singles. It moves bits without arithmetic, so MXCSR is left alone.

Recorded on Zen 5#

• Two sources. vshuff64x2 zmm17{k3}, zmm30, zmm2, 0x96 built blocks 2 and 1 of ZMM30 and blocks 1 and 2 of ZMM2, and with EBh in K3 wrote doubles 0, 1, 3, 5, 6 and 7, keeping 2 and 4.
• Broadcast. vshuff64x2 zmm9{k1}, zmm9, qword bcst [mem], 0xec wrote the one memory double to elements 5 and 7, the bits K1 (A0h) selects.
• 256 bits, zeroing. vshuff64x2 ymm0{k3}{z}, ymm31, ymm16, 0x5f read only bits 1:0 of 5Fh, took the high block of each source, and zeroed double 2, whose mask bit is clear.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_shuffle_f64x2 to VSHUFF64X2, and also __builtin_shufflevector on vectors of eight doubles when it moves whole blocks: reversing them (0x1b), repeating one or joining the high halves of two vectors (0xee). Both repeat one XMM register four times, _mm512_broadcast_f64x2, with vshuff64x2 zmm0, zmm0, zmm0, 0. Clang uses VSHUFF64X2 for the unmasked _mm512_shuffle_f32x4 and _mm512_broadcast_f32x4 as well, where GCC keeps VSHUFF32X4. To repeat a YMM register twice, _mm512_broadcast_f64x4, GCC uses VSHUFF64X2 with 0x44 and Clang VINSERTF64X4, and at 256 bits Clang compiles _mm256_shuffle_f64x2 to the VEX VPERM2F128.

AMD’s Zen 5 latency spreadsheet gives VSHUFF64X2 one macro-op on pipe FP1 or FP2, 3 cycles at 256 bits and 5 at 512, two per cycle, as VSHUFI64X2.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    lane = i // 2
    if VL == 256:
        x = imm8 >> lane & 1      # one bit per lane
    else:
        x = imm8 >> 2 * lane & 3  # two bits per lane
    j = x * 2 + i % 2
    if k1[i]:
        if lane < VL // 256:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFF64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALESD
• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD

All 686 AVX10.1 instructions