VSHUFI32X4

VSHUFI32X4 moves 128-bit blocks exactly as VSHUFI64X2 does, whose page explains the immediate: four 2-bit fields at 512 bits, the low two blocks of the result from the first source and the high two from the second, and one bit per block at 256 bits. Only the element size of the mask and of the broadcast differs: a doubleword each. VSHUFF32X4 is the floating-point name.

A doubleword mask#

With a mask, single doublewords of a block can be written while their neighbours keep the old value. On Zen 5, vshufi32x4 zmm17{k7}, zmm30, zmm2, 0x49 with F2E3h in the low 16 bits of K7 filled block 0 from block 1 of ZMM30, block 1 from its block 2, blocks 2 and 3 from blocks 0 and 1 of ZMM2, but wrote only doublewords 0, 1, 5 to 7, 9 and 12 to 15; doublewords 2 to 4, 8, 10 and 11 of ZMM17 kept their values. At 256 bits, vshufi32x4 ymm5{k3}, ymm5, ymmword ptr [mem], 0x37 used only bits 0 and 1 of the immediate: the high block of YMM5 went low and the high block of memory went high, in the six doublewords that EBh selects. A dword bcst operand repeats one doubleword through all four blocks of the second source.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 keep VSHUFI32X4 for the masked intrinsics, _mm512_mask_shuffle_i32x4 and _mm512_maskz_shuffle_i32x4 and their 256-bit forms. Without a mask, GCC keeps it for _mm512_shuffle_i32x4 and for block moves of int vectors written with __builtin_shufflevector, while Clang emits VSHUFI64X2 for both and VPERM2I128 for the 256-bit _mm256_shuffle_i32x4. Neither folds a broadcast into the instruction: for _mm512_shuffle_i32x4(a, _mm512_set1_epi32(*p), 0x44) GCC broadcasts with VPBROADCASTD first, and Clang uses VPERMT2D with an index vector.

AMD’s Zen 5 latency spreadsheet gives VSHUFI32X4 3 cycles at 256 bits and 5 at 512, two per cycle on pipes FP1 and FP2, as for VSHUFI64X2. Zen 5’s 4 recorded cases cover the register, memory and broadcast forms at both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    lane = i // 4
    if VL == 256:
        x = imm8 >> lane & 1      # one bit per lane
    else:
        x = imm8 >> 2 * lane & 3  # two bits per lane
    j = x * 4 + i % 4
    if k1[i]:
        if lane < VL // 256:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFI32X4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALESH
• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS

All 686 AVX10.1 instructions