VSHUFI64X2

VSHUFI64X2 builds a ZMM register from 128-bit blocks: the low two blocks of the result come from the first source and the high two from the second, each chosen by a 2-bit field of the immediate, bits 1:0 for the lowest block up to bits 7:6 for the highest. Given one register twice, it can put any block anywhere, repeats allowed: 0x1B reverses the four blocks and 0x00 repeats block 0. VSHUFI32X4 moves the same blocks and differs only in the element size of its mask and broadcast; VSHUFF64X2 is the floating-point name.

At 256 bits there are two blocks and one bit each: bit 0 picks the low block from the first source, bit 1 the high block from the second, and bits 7:2 are ignored. Unlike VPERM2I128, it cannot fill the low block from the second source, and it writes zeros only through a zeroing mask.

Masks on quadwords#

The mask selects quadwords, so a masked shuffle can move half-blocks. On Zen 5, vshufi64x2 zmm7{k1}, zmm12, zmm7, 0xb9 with A0h in the low byte of K1 wrote only quadwords 5 and 7, the high halves of blocks 2 and 3, which 0xb9 fills from blocks 3 and 2 of ZMM7: the instruction swapped two quadwords of ZMM7. A broadcast source has four equal blocks; vshufi64x2 zmm7{k5}, zmm12, qword bcst [mem], 0xca wrote the one quadword to elements 5, 6 and 7 and the low quadword of block 2 of ZMM12 to element 0, the elements its mask E1h selects.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile _mm512_shuffle_i64x2 to VSHUFI64X2, and also __builtin_shufflevector on 512-bit vectors when it moves whole blocks: reversing them, repeating one or joining the high halves of two vectors. For the low halves of two vectors Clang uses VINSERTF64X4 instead. Without a mask the element size makes no difference, and Clang compiles _mm512_shuffle_i32x4 to VSHUFI64X2 too and the 256-bit _mm256_shuffle_i64x2 to the VEX VPERM2I128; GCC keeps the names of the intrinsics.

AMD’s Zen 5 latency spreadsheet gives VSHUFI64X2 3 cycles at 256 bits and 5 at 512, two per cycle on pipes FP1 and FP2. Zen 5’s 4 recorded cases cover the register, memory and broadcast forms at both widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    lane = i // 2
    if VL == 256:
        x = imm8 >> lane & 1      # one bit per lane
    else:
        x = imm8 >> 2 * lane & 3  # two bits per lane
    j = x * 2 + i % 2
    if k1[i]:
        if lane < VL // 256:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFI64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRNDSCALESS
• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD

All 686 AVX10.1 instructions