Instruction
VSHUFI64X2
Picks 128-bit blocks of quadwords from the two sources as an immediate selects, the lower half of the result from the first source.
- Extensions
- Forms
- 4 (4 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VSHUFI64X2 zmm {k}{z}, zmm, zmm, imm8
VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 | EVEX.512.66.0F3A.W1 43 /r ib | AVX10.1 or AVX512F |
VSHUFI64X2 zmm {k}{z}, zmm, m512/m64bcst, imm8
VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 | EVEX.512.66.0F3A.W1 43 /r ib | AVX10.1 or AVX512F |
VSHUFI64X2 ymm {k}{z}, ymm, ymm, imm8
VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 | EVEX.256.66.0F3A.W1 43 /r ib | AVX10.1 or AVX512F + AVX512VL |
VSHUFI64X2 ymm {k}{z}, ymm, m256/m64bcst, imm8
VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 | EVEX.256.66.0F3A.W1 43 /r ib | AVX10.1 or AVX512F + AVX512VL |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VSHUFI64X2, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm256_mask_alignr_epi64
__m256i _mm256_mask_alignr_epi64(__m256i W, __mmask8 U, __m256i A, __m256i B, const int imm) |
|
_mm256_maskz_alignr_epi64
__m256i _mm256_maskz_alignr_epi64(__mmask8 U, __m256i A, __m256i B, const int imm) |
|
_mm512_broadcast_i64x2
__m512i _mm512_broadcast_i64x2(__m128i __A) |
|
_mm512_shuffle_i64x2
__m512i _mm512_shuffle_i64x2(__m512i A, __m512i B, const int imm) |
|
_mm512_mask_broadcast_i64x2
__m512i _mm512_mask_broadcast_i64x2(__m512i __O, __mmask8 __M, __m128i __A) |
|
_mm512_mask_shuffle_i64x2
__m512i _mm512_mask_shuffle_i64x2(__m512i W, __mmask8 U, __m512i A, __m512i B, const int imm) |
|
_mm512_maskz_broadcast_i64x2
__m512i _mm512_maskz_broadcast_i64x2(__mmask8 __M, __m128i __A) |
|
_mm512_maskz_shuffle_i64x2
__m512i _mm512_maskz_shuffle_i64x2(__mmask8 U, __m512i A, __m512i B, const int imm) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512F_512 | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
AVX512F_256 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VRNDSCALESS
- VRSQRT14PD
- VRSQRT14PS
- VRSQRT14SD
- VRSQRT14SS
- VRSQRTPH
- VRSQRTSH
- VSCALEFPD
- VSCALEFPH
- VSCALEFPS
- VSCALEFSD
- VSCALEFSH
- VSCALEFSS
- VSCATTERDPD
- VSCATTERDPS
- VSCATTERQPD
- VSCATTERQPS
- VSHUFF32X4
- VSHUFF64X2
- VSHUFI32X4
- VSHUFPD
- VSHUFPS
- VSQRTPD
- VSQRTPH
- VSQRTPS
- VSQRTSD
- VSQRTSH
- VSQRTSS
- VSUBPD
- VSUBPH
- VSUBPS
- VSUBSD
- VSUBSH
- VSUBSS
- VUCOMISD
- VUCOMISH
- VUCOMISS
- VUNPCKHPD
- VUNPCKHPS
- VUNPCKLPD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.