VSHUFPD

VSHUFPD is SHUFPD with a separate destination: in each 128-bit lane, the low double of the result comes from the first source and the high double from the second, each picked by one bit of the immediate, as SHUFPD’s page explains. Unlike VSHUFPS, which applies one immediate to every lane, VSHUFPD gives each lane bits of its own: bits 1:0 for the xmm form, 3:0 for ymm, all eight for zmm, so vshufpd ymm0, ymm1, ymm2, 5 takes the high double of each lane of YMM1 and the low double of each lane of YMM2. Memory needs no alignment, and the destination is zeroed above the vector length. The VEX forms need AVX, ymm included; the EVEX forms (AVX-512F, with AVX512VL below 512 bits, or AVX10.1) add a write mask per double and a broadcast double as the second source. Zen 5’s recorded cases:

• vshufpd ymm8, ymm15, ymm0, 0x9d gave double 1 of YMM15, double 0 of YMM0, then doubles 3 of each: bits 3:0, 1101b, decided, and bits 7:4 played no part.
• vshufpd zmm24{k3}, zmm3, qword bcst [mem], 0x65 wrote the double from memory into elements 1, 3, 5 and 7, the odd positions, doubles of ZMM3’s lanes into elements 0 and 6, and kept elements 2 and 4, which k3 leaves clear.

Swaps and fix-ups#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, the swap _mm_shuffle_pd(a, a, 1) and its ymm twin are VPERMILPD in GCC 14 and VSHUFPD of one register with itself in Clang 23, which also uses vshufpd xmm1, xmm0, xmm0, 1 to bring a high double or a high pair down in horizontal sums. Both compilers swap the real and imaginary parts of a global array of complex doubles with VPERMILPD straight from memory, which VSHUFPD cannot do with one operand in memory. In GCC’s loop at -v3 that builds the complex array from two arrays, VPERMPD spreads the inputs and vshufpd ymm, ymm, ymm, 0xc merges them.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows one macro-op on pipes FP0 to FP3, a latency of 1 cycle and four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    j = i - i % 2 + (imm8 >> i & 1)
    if k1[i]:  # 1 without a write mask
        if i % 2 == 0:
            zmm1.q[i] = zmm2.q[j]
        else:
            zmm1.q[i] = src3.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSUBUSW
• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14PD
• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS

All 686 AVX10.1 instructions