VSHUFPS

VSHUFPS is SHUFPS with a separate destination: the low two singles of each result come from the first source and the high two from the second, each picked by a 2-bit field of the immediate, as SHUFPS’s page explains. The ymm and zmm forms apply the one immediate to every 128-bit lane, and a field picks only within its own lane. Memory needs no alignment, and the destination is zeroed above the vector length. The VEX forms need AVX, ymm included; the EVEX forms (AVX-512F, with AVX512VL below 512 bits, or AVX10.1) add a write mask per single and a second source of one broadcast single. Zen 5’s recorded cases:

• vshufps ymm7, ymm11, ymm7, 0x88 gave elements 0 and 2 of YMM11, then 0 and 2 of YMM7 in the low lane, and elements 4 and 6 of each in the high lane: the even singles of both sources, lane by lane.
• vshufps zmm5{k6}, zmm5, dword bcst [mem], 0x42 wrote the single from memory into elements 2, 7 and 14, where the fields pick the second source, singles of ZMM5’s own lanes into elements 5, 8 and 9, and kept the other ten.

Lanes in compiled code#

In our builds at -O2, splitting a global array of (x, y) pairs into two arrays shows what the lanes cost. With -march=x86-64-v3, Clang 23 takes the even singles with VSHUFPS 88h and the odd ones with DDh, as SHUFPS does, and then puts the quadwords in order with vpermpd ymm, ymm, 0xd8, since each lane holds results of both sources; GCC 14 uses VPERMD and VBLENDPS instead. With -march=x86-64-v4 both use VPERMT2PS, GCC on zmm registers and Clang on ymm. _mm_set1_ps(x), a SHUFPS for the x86-64 baseline, becomes the register form of VBROADCASTSS at -v3.

AMD’s latency spreadsheet for Zen 5 gives VSHUFPS, in its VEX row and its EVEX row alike, one macro-op with a latency of 1 cycle, four per cycle.

In the optimization guide

What the optimization guide says about VSHUFPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Shuffles and lane crossing: Intel’s shuffles share one port, so blends and shuffles done by loads relieve it; Ice Lake and Golden Cove add a second, in-lane one.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    k = imm8 >> 2 * (i % 4) & 3
    j = i - i % 4 + k
    if k1[i]:  # 1 without a write mask
        if i % 4 < 2:
            zmm1.d[i] = zmm2.d[j]
        else:
            zmm1.d[i] = src3.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.f32[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full)

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPSUBW
• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14PS
• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD

All 686 AVX10.1 instructions