x86-64.net

Instruction

VSHUFPS

Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VSHUFPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSHUFPS xmm, xmm, m128, imm8 VSHUFPS_XMMdq_XMMdq_MEMdq_IMMbVEX.128.NP.0F.WIG C6 /r ibAVX
VSHUFPS xmm, xmm, xmm, imm8 VSHUFPS_XMMdq_XMMdq_XMMdq_IMMbVEX.128.NP.0F.WIG C6 /r ibAVX
VSHUFPS ymm, ymm, m256, imm8 VSHUFPS_YMMqq_YMMqq_MEMqq_IMMbVEX.256.NP.0F.WIG C6 /r ibAVX
VSHUFPS ymm, ymm, ymm, imm8 VSHUFPS_YMMqq_YMMqq_YMMqq_IMMbVEX.256.NP.0F.WIG C6 /r ibAVX
VSHUFPS zmm {k}{z}, zmm, zmm, imm8 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512EVEX.512.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F
VSHUFPS zmm {k}{z}, zmm, m512/m32bcst, imm8 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512EVEX.512.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F
VSHUFPS xmm {k}{z}, xmm, xmm, imm8 VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512EVEX.128.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F + AVX512VL
VSHUFPS xmm {k}{z}, xmm, m128/m32bcst, imm8 VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512EVEX.128.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F + AVX512VL
VSHUFPS ymm {k}{z}, ymm, ymm, imm8 VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512EVEX.256.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F + AVX512VL
VSHUFPS ymm {k}{z}, ymm, m256/m32bcst, imm8 VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512EVEX.256.NP.0F.W0 C6 /r ibAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSHUFPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_shuffle_ps __m128 _mm_shuffle_ps(__m128 a, __m128 b, const int mask)

VSHUFPS xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_permute_ps __m128 _mm_mask_permute_ps(__m128 W, __mmask8 U, __m128 X, const int C)

VSHUFPS xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm_mask_shuffle_ps __m128 _mm_mask_shuffle_ps(__m128 W, __mmask8 U, __m128 A, __m128 B, const int M)

VSHUFPS xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_permute_ps __m128 _mm_maskz_permute_ps(__mmask8 U, __m128 X, const int C)

VSHUFPS xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm_maskz_shuffle_ps __m128 _mm_maskz_shuffle_ps(__mmask8 U, __m128 A, __m128 B, const int M)

VSHUFPS xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512vl

_mm256_shuffle_ps __m256 _mm256_shuffle_ps(__m256 a, __m256 b, const int mask)

VSHUFPS ymm, ymm, ymm, imm8 VEX.256 -mavx

_mm256_mask_permute_ps __m256 _mm256_mask_permute_ps(__m256 W, __mmask8 U, __m256 X, const int C)

VSHUFPS ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm256_mask_shuffle_ps __m256 _mm256_mask_shuffle_ps(__m256 W, __mmask8 U, __m256 A, __m256 B, const int M)

VSHUFPS ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_permute_ps __m256 _mm256_maskz_permute_ps(__mmask8 U, __m256 X, const int C)

VSHUFPS ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm256_maskz_shuffle_ps __m256 _mm256_maskz_shuffle_ps(__mmask8 U, __m256 A, __m256 B, const int M)

VSHUFPS ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512vl

_mm512_permute_ps __m512 _mm512_permute_ps(__m512 X, const int C)

VSHUFPS zmm, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_shuffle_ps __m512 _mm512_shuffle_ps(__m512 A, __m512 B, const int M)

VSHUFPS zmm, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_permute_ps __m512 _mm512_mask_permute_ps(__m512 W, __mmask16 U, __m512 X, const int C)

VSHUFPS zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_mask_shuffle_ps __m512 _mm512_mask_shuffle_ps(__m512 W, __mmask16 U, __m512 A, __m512 B, const int M)

VSHUFPS zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_permute_ps __m512 _mm512_maskz_permute_ps(__mmask16 U, __m512 X, const int C)

VSHUFPS zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512f

_mm512_maskz_shuffle_ps __m512 _mm512_maskz_shuffle_ps(__mmask16 U, __m512 A, __m512 B, const int M)

VSHUFPS zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.