Extensions
Forms
2 (2 VEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VSM3MSG1 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSM3MSG1 xmm, xmm, xmm VSM3MSG1_XMMu32_XMMu32_XMMu32VEX.128.NP.0F38.W0 DA /rSM3 + AVX
VSM3MSG1 xmm, xmm, m128 VSM3MSG1_XMMu32_XMMu32_MEMu32VEX.128.NP.0F38.W0 DA /rSM3 + AVX

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSM3MSG1, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sm3msg1_epi32 __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)

VSM3MSG1 xmm, xmm, xmm VEX.128 -msm3

VSM3MSG1 xmm, xmm, xmm VEX.128 -msm3 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SM3

SM3 + AVX
CPUID.(EAX=07H,ECX=1):EAX[1] SM3
CPUID.01H:ECX[28] AVX

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest

More SM3 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.