x86-64.net

Instruction

VSM4RNDS4

Performs four rounds of SM4 encryption in each 128-bit lane.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VSM4RNDS4 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VSM4RNDS4 xmm, xmm, xmm VSM4RNDS4_XMMu32_XMMu32_XMMu32VEX.128.F2.0F38.W0 DA /rSM4 + AVX
VSM4RNDS4 xmm, xmm, m128 VSM4RNDS4_XMMu32_XMMu32_MEMu32VEX.128.F2.0F38.W0 DA /rSM4 + AVX
VSM4RNDS4 ymm, ymm, ymm VSM4RNDS4_YMMu32_YMMu32_YMMu32VEX.256.F2.0F38.W0 DA /rSM4 + AVX
VSM4RNDS4 ymm, ymm, m256 VSM4RNDS4_YMMu32_YMMu32_MEMu32VEX.256.F2.0F38.W0 DA /rSM4 + AVX
VSM4RNDS4 xmm, xmm, xmm VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512EVEX.128.F2.0F38.W0 DA /rSM4 + AVX10
VSM4RNDS4 xmm, xmm, m128 VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512EVEX.128.F2.0F38.W0 DA /rSM4 + AVX10
VSM4RNDS4 ymm, ymm, ymm VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512EVEX.256.F2.0F38.W0 DA /rSM4 + AVX10
VSM4RNDS4 ymm, ymm, m256 VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512EVEX.256.F2.0F38.W0 DA /rSM4 + AVX10
VSM4RNDS4 zmm, zmm, zmm VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512EVEX.512.F2.0F38.W0 DA /rSM4 + AVX10
VSM4RNDS4 zmm, zmm, m512 VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512EVEX.512.F2.0F38.W0 DA /rSM4 + AVX10

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSM4RNDS4, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_sm4rnds4_epi32 __m128i _mm_sm4rnds4_epi32(__m128i A, __m128i B)

VSM4RNDS4 xmm, xmm, xmm VEX.128 -msm4

VSM4RNDS4 xmm, xmm, xmm VEX.128 -mavx -msm4with AVX enabled

_mm256_sm4rnds4_epi32 __m256i _mm256_sm4rnds4_epi32(__m256i A, __m256i B)

VSM4RNDS4 ymm, ymm, ymm VEX.256 -msm4

VSM4RNDS4 ymm, ymm, ymm VEX.256 -mavx -msm4with AVX enabled

_mm512_sm4rnds4_epi32 __m512i _mm512_sm4rnds4_epi32(__m512i __A, __m512i __B)

VSM4RNDS4 zmm, zmm, zmm EVEX.512 -msm4 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SM4

SM4 + AVX
CPUID.(EAX=07H,ECX=1):EAX[2] SM4
CPUID.01H:ECX[28] AVX

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Clearwater Forest
SM4_128

SM4 + AVX10
CPUID.(EAX=07H,ECX=1):EAX[2] SM4
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids
SM4_256

SM4 + AVX10
CPUID.(EAX=07H,ECX=1):EAX[2] SM4
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids
SM4_512

SM4 + AVX10
CPUID.(EAX=07H,ECX=1):EAX[2] SM4
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids

More SM4 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.