VSQRTPD

VSQRTPD takes the square roots of two, four or eight doubles. It is SQRTPD in VEX and EVEX encodings; VSQRTPS covers what the encodings add, and why C’s errno keeps a loop over sqrtf scalar. The same holds for sqrt: GCC 14 and Clang 23 at -O2 test each argument and call the library for a negative one, and only with -fno-math-errno emit VSQRTPD. Unlike for floats, -ffast-math adds no estimate: 1.0 / sqrt(b[i]) stays VSQRTPD and VDIVPD for -march=x86-64-v3, x86-64-v4 and znver5 alike.

Edges recorded on Zen 5#

• The root of -0 was -0, and that of +infinity +infinity; any other negative number, -infinity included, gave the indefinite FFF8000000000000H and set IE.
• A square root never underflows: that of the smallest denormal, 2^-1074, was the normal 2^-537 (1E60000000000000H), with only the denormal flag set.
• DAZ matters for a negative denormal. Without it, the root of -2^-1023 was the indefinite; with DAZ set, that input counted as -0 and its root was -0.
• The rounding mode reaches the last bit. The root of 1.0000000000000002, the double after 1, was 1 under round to nearest and 1.0000000000000002 under {ru-sae}; that of 0.1 ended in …490FH rounding toward zero and in …4910H rounding up.

On Zen 5#

AMD’s Zen 5 guide gives VSQRTPD a latency of 20 cycles and a throughput of 0.133 per cycle at every width, against 14 cycles and 0.222 for VSQRTPS, in the divide unit on pipe FP1 that VDIVPD uses too.

In the optimization guide

What the optimization guide says about VSQRTPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• AVX2 and FMA: Apart from division, square root, AES and the SSE4.2 string compares, the vector units are 256 bits wide. sources differ

Skylake to Cooper Lake

• Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.f64[i] = sqrt(src2.f64[i])
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src2.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPS
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPH
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions