VSQRTPH

VSQRTPH takes the square root of each half-precision element, 32 per zmm register, and rounds each root correctly under MXCSR.RC, or under {er} on the 512-bit register form. It is VSQRTPS for halves, with the special inputs that SQRTPS’s page lists: the root of -0 is -0, and any other negative input is invalid. The encoding is NP 51h in EVEX map 5, SQRTPS’s byte in FP16’s map, with masking and a source broadcast from one half in memory. A root can neither overflow nor underflow, so Intel’s entry lists only invalid, precision and denormal. VADDPH covers the format, the CPUID bits and FP16’s use of MXCSR; VSQRTSH is the scalar form.

Estimates instead#

Intel’s optimization manual counts the square root among the FP16 operations that are correctly rounded (Section 18.5.3), and offers two cheaper routes for code that can give that up. x times the estimate of VRSQRTPH matches VSQRTPH for 70% of inputs and is never off by more than 1 ULP (Section 18.5.9). For 1/sqrt(x) the estimate alone is better than VSQRTPH followed by VDIVPH: the manual gives the pair 48 cycles at 512 bits against 6 for VRSQRTPH, and finds the pair less accurate (Section 18.5.8.3).

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16 and -fno-math-errno, GCC 14 and Clang 23 compile c[i] = __builtin_sqrtf16(a[i]) over global _Float16 arrays to VSQRTPH with the source in memory, GCC on zmm and Clang on ymm registers. Without that option both keep the loop scalar for C’s errno, as SQRTPS’s page explains: GCC tests each VSQRTSH result for a NaN and Clang calls sqrtf16. GCC also turns (_Float16)sqrtf(a[i]), a root taken in single precision, into VSQRTPH, while Clang widens with VCVTPH2PSX, takes VSQRTPS and narrows again. -ffast-math keeps VSQRTPH in both, where GCC’s loop over singles switches to an estimate, and turns 1 / sqrt into VRSQRTPH alone.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VSQRTPH.

In the optimization guide

What the optimization guide says about VSQRTPH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: AVX-512 FP16 adds and multiplies 32 half-precision values per 512-bit register with a latency of four cycles; division and square root take about 31. sources differ

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.f16[i] = sqrt(src2.f16[i])
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# m16bcst: src2.f16[i] is the m16 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions