VSQRTPS

VSQRTPS is SQRTPS in VEX and EVEX encodings. The SQRTPS page covers the special inputs, C’s errno and the history of its speed; the VEX forms add a separate destination and 256 bits, the EVEX forms 512 bits, masking, a broadcast single and a rounding mode given in the instruction. On Zen 5, {ru-sae} took the root of 2 to 1.41421366, the single just above the true value, where rounding to nearest gives 1.41421354, and set no flag although the result was inexact.

What compilers emit#

The loop a[i] = sqrtf(b[i]) stays scalar at -O2 in GCC 14 and Clang 23 unless errno is out of the way. With -fno-math-errno it becomes VSQRTPS on ymm registers for -march=x86-64-v3, on zmm for -march=znver5, and for -march=x86-64-v4 on zmm in GCC and ymm in Clang. A reciprocal root, 1.0f / sqrtf(b[i]), becomes VSQRTPS and VDIVPS for each of these targets.

-ffast-math lets them use an estimate instead, and here the compilers part ways:

• For -march=x86-64-v3, both compute the root as x times VRSQRTPS’s estimate of 1/sqrt(x), refined by one Newton-Raphson step with an FMA, and add a compare and a VANDPS so that 0 still gives 0 rather than 0 times infinity, a NaN.
• For -march=x86-64-v4 and znver5, GCC does the same with VRSQRT14PS on zmm registers, while Clang keeps VSQRTPS.

Intel’s manual bounds the relative error of the two estimates by 1.5 times 2^-12 and by 2^-14, and the refined results are close but not correctly rounded, so a -ffast-math build can give different last bits from one without it, and GCC’s from Clang’s.

On Zen 5#

AMD’s Zen 5 guide lists VSQRTPS with a latency of 14 cycles and a throughput of 0.222 per cycle at every width, in the same divide unit as VDIVPS (Section 2.11.1).

In the optimization guide

What the optimization guide says about VSQRTPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• AVX2 and FMA: Apart from division, square root, AES and the SSE4.2 string compares, the vector units are 256 bits wide. sources differ

Skylake to Cooper Lake

• Vectors on all parts: Division and square root are pipelined, and 256-bit forms have the latency of 128-bit ones: LLVM’s models give DIVPS 11 cycles, SQRTPS 12, DIVPD 14 and SQRTPD 18.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.f32[i] = sqrt(src2.f32[i])
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# m32bcst: src2.f32[i] is the m32 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTSD
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTSD
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions