VSQRTSD

VSQRTSD is SQRTSD in VEX and EVEX encodings: the root of the low double of its last operand, with the high double copied from the operand before it and the bits above 127 cleared. VSQRTSS covers what the encodings add, from the named source of the upper element to masking and a rounding mode on xmm registers; the SQRTSD page covers C’s sqrt and its errno test.

Which register gives the high double#

In Zen 5’s recorded vsqrtsd xmm8, xmm15, xmm0, under MXCSR 3FC0H (round down, DAZ set), XMM0 held -1 below and 2 above. The result was the indefinite FFF8000000000000H, with IE set, below and the high double of XMM15 above: the source of the root gives only its low element.

That operand order is the one of the intrinsic. _mm_sqrt_sd(a, b) returns the root of the low double of b with the high double of a, and Clang 23 compiles it to a single vsqrtsd xmm0, xmm0, xmm1 with -march=x86-64-v3 or x86-64-v4, while GCC 14 still copies the low double over with VMOVSD first and then takes the root in place, as it does for SQRTSD. For sqrt(x) both emit vsqrtsd xmm0, xmm0, xmm0 after the test for a negative x.

Suppressed exceptions#

Zen 5’s EVEX cases:

• vsqrtsd xmm7{k7}, xmm12, xmm7, {rz-sae}, with bit 0 of K7 set, took the root of -1 while MXCSR (6600H) left the invalid exception unmasked. The result was the indefinite, with no #XM and no flag set: {sae} suppresses both.
• Without it, vsqrtsd xmm0{k4}{z}, xmm31, qword ptr [mem] took the root of -infinity under FFC0H and gave the indefinite with IE set, the high double coming from XMM31, a register only EVEX can name.

AMD’s latency spreadsheet for Zen 5 lists it at 20 cycles and 0.133 per cycle on pipe FP1, against 14 cycles for VSQRTSS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.f64[0] = sqrt(src3.f64[0])
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {er}: the form's rounding, not MXCSR.RC, and no flags
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VSQRTSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPTEST
• VPUNPCKHBW
• VPUNPCKHDQ
• VPUNPCKHQDQ
• VPUNPCKHWD
• VPUNPCKLBW
• VPUNPCKLDQ
• VPUNPCKLQDQ
• VPUNPCKLWD
• VPXOR
• VRCPPS
• VRCPSS
• VROUNDPD
• VROUNDPS
• VROUNDSD
• VROUNDSS
• VRSQRTPS
• VRSQRTSS
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPS
• VSQRTSS
• VSTMXCSR
• VSUBPD
• VSUBPS
• VSUBSD
• VSUBSS
• VTESTPD
• VTESTPS
• VUCOMISD
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS
• VZEROALL
• VZEROUPPER

All 253 AVX instructions

More AVX10.1 instructions

• VRSQRT14SD
• VRSQRT14SS
• VRSQRTPH
• VRSQRTSH
• VSCALEFPD
• VSCALEFPH
• VSCALEFPS
• VSCALEFSD
• VSCALEFSH
• VSCALEFSS
• VSCATTERDPD
• VSCATTERDPS
• VSCATTERQPD
• VSCATTERQPS
• VSHUFF32X4
• VSHUFF64X2
• VSHUFI32X4
• VSHUFI64X2
• VSHUFPD
• VSHUFPS
• VSQRTPD
• VSQRTPH
• VSQRTPS
• VSQRTSH
• VSQRTSS
• VSUBPD
• VSUBPH
• VSUBPS
• VSUBSD
• VSUBSH
• VSUBSS
• VUCOMISD
• VUCOMISH
• VUCOMISS
• VUNPCKHPD
• VUNPCKHPS
• VUNPCKLPD
• VUNPCKLPS
• VXORPD
• VXORPS

All 686 AVX10.1 instructions